Bug with PE generation of PDB error clearing (K52)

[ryanjohnson]

I stumbled into a problem when if I set the ADC channel to 31 (disabled), I was unable to get the ADC to work again unless resetting the processor, even with a re-init of the ADC controller, PDB, and DMA. What I found was that the PDB0_Init code generated by PE performs the following:

PDB0_CH0S = (PDB_S_CF(0x00) | PDB_S_ERR(0xFF));

I halted in the debugger after calling the init function and noticed the error was still set. The description of the register field in the debugger reads:

ERR bits[  7:0  ] = 1

Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.

I tried manually writing '1's' to the field, but the bit was still set. I found in the reference manual however: "Writing 0’s to clear the sequence error flags.". Sure enough writing 0's cleared the error and allowed me to move from disabled to an active channel.

[Robin_Shen]

May be you are reading K52P144M100SF2RM .

You can find "Writing 0’s to clear the sequence error flags" in K52P144M100SF2V2RM.

[ryanjohnson]

Correct, and that's my point. The RM says to write 0's to clear the error, and that is right based on my testing. However the PE generated code writes 1's to clear the error (which has no effect) and the description in the debugger also is incorrect by stating to clear the error by writing 1's.

[mjbcswitzerland]

Hi

I have recently been working with PDB and ADC and found that an ADC trigger overrun causes the PDB channel's error bit to be set (when the last value has not been read out in time). However it hasn't been possible to reset this error (writing either '0' or '1' hasn't helped) so it was presumed that the ADC needs to be completely reset (as well).

This point is presently open and will probably be worked on again next week, but it may point to a basic difficulty in clearing the error bits which is not clearly documented. I'll be watching thsi thread in case somethin new comes to light or may comment again if a solution can been found.

Regards

Mark