ryanjohnson

Bug with PE generation of PDB error clearing (K52)

Discussion created by ryanjohnson on Sep 25, 2013
Latest reply on Sep 26, 2013 by Mark Butcher

I stumbled into a problem when if I set the ADC channel to 31 (disabled), I was unable to get the ADC to work again unless resetting the processor, even with a re-init of the ADC controller, PDB, and DMA. What I found was that the PDB0_Init code generated by PE performs the following:

 

PDB0_CH0S = (PDB_S_CF(0x00) | PDB_S_ERR(0xFF));

 

I halted in the debugger after calling the init function and noticed the error was still set. The description of the register field in the debugger reads:

 

ERR bits[  7:0  ] = 1Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags.

 

I tried manually writing '1's' to the field, but the bit was still set. I found in the reference manual however: "Writing 0’s to clear the sequence error flags.". Sure enough writing 0's cleared the error and allowed me to move from disabled to an active channel.

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