How can a slave force the I2C SCL line low for an adjustable time up to 5 ms?
A MK10DX64VFM5 is acting as an I2C. It receives a command from the I2C master, followed by the master immediately reading the slave address for a response. For some messages, the MK10DX64VFM5 slave needs additional time to form a response. Clock stretching seems like an ideal solution but how to force SCL low and release it when desired is not clear from the manual.