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i.MX6Q arm_dcache_invalidate() bug?

Question asked by Andrew Trotman on Sep 10, 2013
Latest reply on Sep 11, 2013 by Andrew Trotman

According to "ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition", section "B4.1.19 CCSIDR, Cache Size ID Registers, VMSA", NumSets is in bits 13-27.  The source code that is shipped with the i.MX6Q Platform SDK uses 0x13 not 13.  Is this a bug or am I missing something?  The Freescale code is listed below


Thanks

Andrew.



void arm_dcache_invalidate()

{

    uint32_t csid;    // Cache Size ID

    uint32_t wayset;  // wayset parameter

    int num_sets; // number of sets 

    int num_ways; // number of ways

 

    _ARM_MRC(15, 1, csid, 0, 0, 0);    // Read Cache Size ID

   

    // Fill number of sets  and number of ways from csid register  This walues are decremented by 1

    num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT)

   

    // Invalidation all lines (all Sets in all ways)

    while (num_ways >= 0)

    {

        num_sets = (csid >> 0x13) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT)

        while (num_sets >= 0 )

        {

            wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT)

            // invalidate line if we know set and way

            _ARM_MCR(15, 0, wayset, 7, 6, 2);

            num_sets--;

        }

        num_ways--;

    }

   

    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete

    _ARM_DSB();

}

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