I'm trying to enable PL310 L2 Cache event monitoring on i.MX6 sabrelite and i get zeroed out PMU counters. The "CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual" part "2.5.8 Cache event monitoring" says "When the signal on the SPNIDEN pin is LOW the event bus and event counters only output or count non-secure events.". I'm reading SPNIDEN value using Debug Control Register and i get zero.
The Cortex -A9 Technical Reference Manual (Revision: r4p1) in part "10.8.3 Changing the authentication signals" says "The NIDEN, DBGEN, SPIDEN, and SPNIDEN input signals are either tied off to some fixed value or controlled by some external device.".
I find no reference for these signals in the "i.MX 6Dual/6Quad Applications Processor Reference Manual".
It is there any way to enable input signals on the board?