Case: Say, all the 8 cores in P4080 result in L1 and L2 cache miss at the same time, leading to Main memory read request with all read requests having the same timestamp
Question: How does the CoreNet Coherency fabric order arbitrate/order the requests(having the same timestamp)?
Could someone please guide me to the right document about CoreNet Fabric and arbitration w.r.t. Memory Controller. I could not find one.