Jeffrey Dungen

Variable PORTAB read/store execution time in NE64?

Discussion created by Jeffrey Dungen on Jul 18, 2007
Latest reply on Jul 19, 2007 by Jeffrey Dungen
We have an NE64 connected to an FPGA for data transfer.  We transfer 16-bit words from the FPGA to the NE64 via PORTAB, using our own handshaking scheme implemented in software on PORTE.  When the handshaking completes, the FPGA just sends 16-bit word after word, every X clock cycles.  The FPGA uses the ECLK from the NE64 for the transfer.  The NE64 is in Normal Single Chip mode with NECLK = 0.

The code on the NE64 is the following (minus the handshaking):

      SEI                // Disable interrupts
      LDX   PointerTo16bitWideBuffer  // Load buffer address
      LDD   _PORTAB      // Load 16-bit word to register
      STD   0,X          // Copy register to buffer
      LDD   _PORTAB      //   etc...
      STD   2,X
      LDD   _PORTAB
      STD   4,X

Given that it's just a bunch of LDD and STD instructions, I'd expect each of these instruction pairs to take a FIXED number of clock cycles.  But this doesn't seem to be the case.  If for example the FPGA sends (0, 1, 2, 3, 4, 5, 6, 7, etc.) leaving each unchanged for three clock cycles, the NE64 "stores" this as (0, 1, 2, 3, 4, 5, 7, etc.), with 6 missing.  :smileysad:

If I repeat the same procedure with the FPGA leaving the data unchanged for 1, 2, 3, 4, 5, 6, 7 clock cycles, I always run into missing or duplicated codes.  No constant number of cycle transfer system works!

A hack that I made which works keeps each code active for the following number of clock cycles:
3, 6, 2, 6, 6, 6, 6    Aaaaah!

So my question is: what is going on?  Is the NE64 really taking a variable number of clock cycles to execute the LDD and STD pairs?

I've tried playing with the bus cycle stretching settings without success (they shouldn't do anything anyway).