On a KL15x we are using the SPI at 2Mhz (i.e. SPI periperhal clock / spi clk = 2 Mhz). The core is running at 48Mhz and the bus clock at 24Mhz. We are using the DMA to push data into the SPI tx register. It seems to work but there is a short, fixed length, delay between bytes. It amounts to around 250ns - or about 12 system clock cycles.
1. What can be the cause of this delay?
When the DMA writes to the SPI tx register, I assume that in one cycle that is shifted into the Tx buffer (which is used to shift out the data serially at the SPI clk). But instantly after moving the data to the Tx bufferthe SPI will assert its request to the DMA. My question boils down to asking how long will it take the DMA to resolve the request and read data from RAM and then write it back into the SPI Tx register. Bear in mind that the SPI is running at 2Mhz so it will take it 4micro seconds to shift out the full byte. This should give the DMA plenty of time to have retrieved and written the next byte. I don't understand the delay?