Hello

I am trying to vary the PWM duty-cycle based on an ADC value.PWM frequency is 16khz

What i am trying to achieve is keep an output current constant by driving MOSFETs through a QG8.An ADC channel measures this current value.

What i see is that the duty-cycle remains unchanged even when ADC values change.

I think i am doing a very basic mistake , someone please correct me..writing init and ISR codes here

**#define TIMER_OVERFLOW 60 // us**

**interrupt 7 void TimerCH1 (void)**

**{**

** // Stops Timer1**

** TPMSC = TIMER_STOP; **

** if(current_adjust>512) // 1.5v corresponds to 5A**

** {**

** duty_cycle_variation--;**

** if(duty_cycle_variation<=1)duty_cycle_variation=1;**

** }**

** if(current_adjust<512)**

** {**

** duty_cycle_variation++;**

** if(duty_cycle_variation>=100)duty_cycle_variation=100;**

** }**

** TPMC1V = duty_cycle_variation;**

** // Restarts Timer1**

** TPMSC = TIMER_START; **

**}**

**void Timer1_init(void)**

**{**

** // Timer1 period **

** TPMMOD = TIMER_OVERFLOW; //15ms**

**//Initial duty cycle **

** TPMC1V=0;**

** // Selects PWM Low-true pulses in the Timer1 Channel0 (PTA0/TPM1CH0) **

** TPMC1SC = 0x028; //flag=0|ch_int_dis=0|MSnBA=10=edge aligned PWM|ELSBA=01=set o/p on compare|00**

** // Starts Timer1 ELSBA=10=clr o/p on compare**

** //TPMSC = TIMER_START; //0,TOIE=1,CPWMS=0,CLKSAB=01 PS2-0=011(div/8=1us)**

** }**

Someone please help

Thanks and regards

Hello,

There are a few factors that you need to take into account -

One possible approach to synchronise the ADC and PWM operation would be to utilise the TPM overflow interrupt. Within the ISR code, the previous ADC conversion would be read, and a new ADC conversion started. The result just obtained would then be processed to update the TPMC1V register. Since the actual PWM duty would udate just prior to the next overflow, the control would lag by at least one PWM period. However, you would need substantial filtering, over many PWM periods, to sense the average load current.

Assume you were using a bus frequency of 10 MHz and an ADC clock of 5 MHz. With short sampling interval, the ADC conversion time would be equivalent 45 bus cycles. To this you would need to add the number of cycles required to enter the ISR, plus the cycles for reading of the previous result and starting the new conversion. The minimum PWM period should be somewhat greater than this value, provided the additional cycles to complete and exit the ISR does not exceed 45 cycles.

It is also possible that the occurrence of other interrupts may affect the stability of your control system.

Regards,

Mac