I have set the 'Pre' and 'Post' SCK delay to 4 (b01) which takes care of PCS delay before and after SCK. However while accessing a second chip on the same SPI bus, immediately with another PCS, causes the delay problems wherein the another chip select goes permanently low. This is worked around using a simple for() delay loop between two transactions.
However that is non-portable. Is there any bit which I can poll to check the completion of the internal delay (post) and the respective PCS has gone high. Also this post delay is affecting the performance of the software wherein the lowest delay is 2 bus-clocks without prescalars.