i got "dma error" when use "nand read" in uboot, below is my context:
hardware: imx6q
nandflash: micron 29F32G08CBAAAWP
software version: L3.0.35_1.1.0
debug log:
**********************************************************************************************
U-Boot 2009.08-dirty (Mar 19 2013 - 17:04:22)
CPU: Freescale i.MX6 family TO1.1 at 792 MHz
Temperature: 35 C, calibration data 0x5924ff7d
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock : 66000000Hz
ipg per clock : 66000000Hz
uart clock : 80000000Hz
cspi clock : 60000000Hz
ahb clock : 132000000Hz
axi clock : 264000000Hz
emi_slow clock: 132000000Hz
ddr clock : 528000000Hz
usdhc1 clock : 198000000Hz
usdhc2 clock : 198000000Hz
usdhc3 clock : 198000000Hz
usdhc4 clock : 198000000Hz
nfc clock : 11000000Hz
Board: i.MX6Q-SABRESD: unknown-board Board: 0x63011 [POR ]
Boot Device: SD
I2C: ready
DRAM: 1 GB
NAND: ONFI param page 0 valid
ONFI flash detected
Manufacturer ID: 0x2c, Chip ID: 0xd7 (Micron MT29F32G08CBAAAWP), page size: 4096, OOB size: 218
4096 MiB
MMC: FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2,FSL_USDHC: 3
In: serial
Out: serial
Err: serial
Found PFUZE100! deviceid=10,revid=11
Net: got MAC address from IIM: 00:00:00:00:00:00
FEC0 [PRIME]
Hit any key to stop autoboot: 0
MX6Q SABRESD U-Boot >
MX6Q SABRESD U-Boot >
MX6Q SABRESD U-Boot >
MX6Q SABRESD U-Boot >
MX6Q SABRESD U-Boot >
MX6Q SABRESD U-Boot >
MX6Q SABRESD U-Boot > nand read 0x10800000 0x1000000 0x400000
NAND read: device 0 offset 0x1000000, size 0x400000
[read_page] DMA error
[read_page] bch timeout!!!
[gpmi_nfc_ecc_read_page] Error in ECC-based read: -110
NAND read from offset 1000000 failed -110
0 bytes read: ERROR
MX6Q SABRESD U-Boot >
***************************************************************************************************
hope someone can give me suggestion.
has solved this problem, just follow this patch:
board/freescale/mx6q_sabresd/mx6q_sabresd.c in uboot.
iomux_v3_cfg_t nfc_pads[] = {
@@ -947,11 +947,11 @@ int board_eth_init(bd_t *bis)
* that is required for UHS-I mode of operation.
* Last element in struct is used to indicate 1.8V support.
*/
-struct fsl_esdhc_cfg usdhc_cfg[4] = {
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC1_BASE_ADDR, 1, 1, 1, 0},
{USDHC2_BASE_ADDR, 1, 1, 1, 0},
{USDHC3_BASE_ADDR, 1, 1, 1, 0},
- {USDHC4_BASE_ADDR, 1, 1, 1, 0},
+ /* {USDHC4_BASE_ADDR, 1, 1, 1, 0}, */
};
#ifdef CONFIG_DYNAMIC_MMC_DEVNO
@@ -1081,11 +1081,11 @@ int usdhc_gpio_init(bd_t *bis)
sizeof(usdhc3_pads) /
sizeof(usdhc3_pads[0]));
break;
- case 3:
- mxc_iomux_v3_setup_multiple_pads(usdhc4_pads,
- sizeof(usdhc4_pads) /
- sizeof(usdhc4_pads[0]));
- break;
+ /* case 3: */
+ /* mxc_iomux_v3_setup_multiple_pads(usdhc4_pads, */
+ /* sizeof(usdhc4_pads) / */
+ /* sizeof(usdhc4_pads[0])); */
+ /* break; */
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",