We are using MC9S08DZ60 processor in our project. I am trying to conduct RAM integrity checks starting from 0x0080 to 0x107F only during powerup soon after entering main loop before enabling the interrupts. RAM integrity algorithm works something like this. It saves existing two bytes of data, writes the actual 2 byte address into the same location as data and reads it back to compare with the address. Hardware vulnerabilities observed during bench testing. Continuous read and write operations of contiguous RAM locations prevents write access after specific number of continuous write cycles. The failure after specific number of write cycles remains same in any power cycle. This failure to write the data sets a fault as my algorithm checks the data which is written and compares it with the address. While single read or write operation at a time doesn’t create above failure condition when tried through debugger.
Any ideas for this behaviour.