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IPU v3  CSI0, HSYNC and DATA_EN questions in gated clock mode.

Question asked by Jim Malone on Oct 26, 2012
Latest reply on Nov 1, 2013 by ZHU YANG
Branched to a new discussion

Hi All,

 

We are struggling with a 16 bit parallel camera interface hooked up to CSI0 on an i.mx6Solo.

 

We have the data lines hooked up to CSI0_DAT[19:4] with the MSB hooked to 19.  We are providing PIXCLK, VSYNC and HSYNC.

 

First question:

HSYNC is shown as being used as a line valid type signal in the Datasheet (Section 4.11.10.2.2 Rev D of the consumer datasheet - similar section for i.mx53).  So it is active high when data is valid per line.  In the Reference manual, (Section 37.4.3.6.1, Rev B of the i.mx6 Solo/DL Reference manual), it shows HSYNC as a single active high pulse with a width of a single pixclk cycle.  We are assuming that the CSI engine is only looking for the rising edge but would like clarification if anyone knows.  I have also checked the i.mx53 documentation and it has the same discrepancy.

 

Second question:

Is the CSI0_DATA_EN used at all in this interface when in parallel mode?  I can not find much information on the use of this pin at all in the i.mx6 documentation or the i.mx53 documentation.  This signal is used in the MIPI CSI2 mode and routed through the CSI2IPU gasket.  I know this gasket is not used in the parallel mode, but it is the only reference (as well as a timing diagram for data_en) in the entire reference manual.  The reason I ask is we were not driving it (our camera data is passed through an FPGA which drives the CSI0 port) and the FPGA had the pin tristated.  We assumed that a week pullup was pulling this signal high the entire time.  In this mode we are clocking data in, but see blanking data in the active areas when looking at the memory buffers output from the IDMAC.  We then tied the data_en high for the entire operation and saw no change in what we were reading.  Same result on the output.  We tied it low and saw no video sampled at all.  Our FPGA guy then put some logic in to make it work like the gasket layer where the VSYNC fires, Data_en fires, then HSYNC fires, with data_en and HSYNC repeating for each line.  Data_en was off during blanking.  The result was no video sampled.  So needless to say we are all confused by this last result.

 

I have asked my local FAEs but one is out on travel right now.

 

Any help would be greatly appreciated.

Thanks,

Jim

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