Hi bernd,
External bus cycle can be terminated either externally (external /TA signal) or internally (/TA generated internally).
Chip select control register is used to set up transfer acknowledge.
CSCRn[AA] = 0
means a bus cycle is terminated externally. /TA input pin of MCF523X should be connected with /TA signal of an external device.
CSCRn[AA] = 1
CSCRn[IWS] = 0xF (15 wait states)
means /TA is asserted internally as specified by CSCRn[IWS]. An external /TA is not needed.
However, if an external /TA is connected, and external device asserts an external /TA before the wait state countdown asserts the internal /TA, the cycle is terminated.
Every external bus cycle is monitored by a bus monitor by default after reset.
The bus monitor timeout is set according to CCR[BMT] bits (65536 system clocks by default).
If a bus cycle is not terminated withing the time period defined by CCR[BMT] bits, the bus cycle is terminated by bus monitor, if enabled.
Chip select cotrol register is described in the MCF5235 Reference Manual, Chapter 16.
CCR register is described in MCF5235 Reference Manual, Chapter 9
Martin