All 9S08 MCUs have a final division by 2 to derive the bus clock. This of course is after any dividers or prescalers (e.g., RDIV, BDIV, etc) are applied. In other words, if all prescalers are set to divide by 1, the final bus clock will be exactly half the original clock (or FLL derived clock, ICSOUT, or ICGOUT). If you look at the block diagrams, there is always a /2 block right before the BUSCLK
With a 4MHz clock you can't get any higher than 2MHz bus.