Simon Frey

DDR Display clock for the parallel display interface ?

Discussion created by Simon Frey on Nov 29, 2011
Latest reply on Dec 19, 2011 by Yanfei Sun



is there a way to generate a DDR pixel clock for the parallel display port? 

I need to connect a UXGA LCD Display which has an even and an odd LVDS inteface. Each running at 85MHz. So if i configure the DI to output data at 170MPixels/sec with a 85MHz  clock instead of 170MHz, i could latch the even pixels in a buffer at rising edge from this clock and send the buffered even pixel and the actual odd pixel at falling egde through LVDS transmitters.


So to summarize, is there a way to change the SDR Display port clock to a DDR one for the same Pixel rate?


Thank you in advance