Hello, we are working on a project that requires gathering the information from many external ADC at a high bitrate. To be precise, the ADC generate a stream of 38 Mbps.. we must gather at least half a second of this data (18Mb) and process it in about 4 seconds.
We first though about using the GPIO pins but that went out the window since they turn out to be pretty slow, so we have been working on another hipotesis. I'll explain it and I would appreciate if people would give me their opinion.
Our idea was to hang an FPGA from the WEIM controller (sharing the bus with the SDRAM(DDR2) and others). This FPGA would gather all the info (18Mb) and then generate an interrupt to the SDMA controller. The DMA would then performe a transaction from the FPGA to the SDRAM.
Do you think this can actually be done? We know we would have to configure the CSx in order to move at a pace the FPGA could follow, but are there any other issues we are not considering?
I would also appreciate if people with experience hanging stuff from the WEIM controller could chip in. I mean... what type of memory/interface should we emulate with the FPGA? which is the fastest?
Thanks a lot for your time :)