Gathering ADC data i.mx25

[albert_arquer]

Hello, we are working on a project that requires gathering the information from many external ADC at a high bitrate. To be precise, the ADC generate a stream of 38 Mbps.. we must gather at least half a second of this data (18Mb) and process it in about 4 seconds.

We first though about using the GPIO pins but that went out the window since they turn out to be pretty slow, so we have been working on another hipotesis. I'll explain it and I would appreciate if people would give me their opinion.

Our idea was to hang an FPGA from the WEIM controller (sharing the bus with the SDRAM(DDR2) and others). This FPGA would gather all the info (18Mb) and then generate an interrupt to the SDMA controller. The DMA would then performe a transaction from the FPGA to the SDRAM.

Do you think this can actually be done? We know we would have to configure the CSx in order to move at a pace the FPGA could follow, but are there any other issues we are not considering?

I would also appreciate if people with experience hanging stuff from the WEIM controller could chip in. I mean... what type of memory/interface should we emulate with the FPGA? which is the fastest?

Thanks a lot for your time :) 

[FlorentAuger]

Hi,

1. On that page 38, that's not correct, thanks for the catch. The datasheet specifies the min period for the CSPI serial clock at 60.2ns => 16.66MHz => 16.66Mbps. Sorry, 25Mbps was an error, and I was confused with the capability of another i.MX.

2. The access to the SDRAM are always performed at the standard speed for a bus at 133MHz. But the fact that the signals are shared makes the SDRAM unusable during the access to the WEIM bus.

So, the more the WEIM is used, the less the SDRAM can be accessed.

3. Sorry, the notation wasn't very appropriate. It is actually "2.375M words of 16-bit per second" = 38Mbps = 4.75Mbytes/s => 2.375M accesses per second.

4. Same calculation than above from the number you gave: 38Mbps = 4.75Mbytes/s.

[albert_arquer]

Hi, thanks for your extensive reply and sorry about the delay.

Unfortunatelly we have decided not to use a i.mx processor for this applications as it didn't feel right to be using it for industrial purposes and the risk/uncertainty was too big. However I would like to comment on your reply as we might still use a i.mx processor in other applications.

1. You said the SPI's max speed is 25mbps but on the i.MX25 page 38 (1-2), near the end, it says that each of the CSPI can go up to 52 Mbps, is this correct or is there something I am not taking into account?

2.You said that the data rate on the WEIM could slow down the whole system... I understand that the WEIM is going to access the external memory slower than the ESDRAM controller accesses the DDR, however, the DDR throughput itself would not be affected right? It would be a matter of configuring the right time constants for a precise chip select in the WEIM's memory space right?

3. I don't get this calculation: "The interface could be used in 16-bit mode => ~2.375MB/s (used bandwidth for 38Mbps)" and this one either "The interface could be used in 32-bit mode (addr and data muxed) => ~1.1875MB/s (used bandwidth for 38Mbps)." could you elaborate on them a little bit?

4. I don't get how you get the this conclusion when considering the use of the CSI: "The datarate would be ~4.75MB/s"

Thanks a lot for your time and sorry if these questions seemed a little dumb to you.

Again, thanks!

PS: I would also appreciate it if you could drop by another thread I have had running for a while. http://imxcommunity.org/forum/topics/kernel-panic-i-mx25?xg_source=activity 

[FlorentAuger]

Hello

The SPI (max ~25mbps) and SSI (~12mps) would be too slow.

The WEIM is a first option with a FPGA. The interface could be used in synchronous mode.The drawback is that the WEIM is considered as a "slow bus" compare the DDR interface. As you mentioned, it shares signals with the DDR interface, so you'll have to make sure that the datarate on the WEIM does not slow down the whole system.

The interface could be used in 16-bit mode => ~2.375MB/s (used bandwidth for 38Mbps) which is finally very small compare to the ideal bandwidth of the WEIM 133MB/s @ 66MHz / (it does not take into account the real timings and time between bursts).

The interface could be used in 32-bit mode (addr and data muxed) => ~1.1875MB/s (used bandwidth for 38Mbps).

I would also suggest to look into the CSI interface, if not used. That's a simple 8-bit synchronous interface that uses less signals and has its own DMA to transfer the data. It samples 8-bits per clock cycles. There are far less things to program compare to the WEIM + SDMA solution. In short, it's an always active interface, and it could capture data only when HSYNC is active, which could be under the control of the FPGA.

The datarate would be ~4.75MB/s, which is about 10 times lower than what the CSI can theoretically "eat" !

[JerryFan]

I don't know the interface type the customer used. But I think nor-flash-like interface is the easiest to be implemented.  

The maximum frequency depends on the WEIM interface of imx25 and the FPGA timing. 

[albert_arquer]

Thanks for your reply Jerry Fan.

Do you have any more info about that? I mean, what interface configuration should we use?

Also, how do I know the maximum frequency that we can achieve reading through the WEIM?

[JerryFan]

The WEIM interface should work for this case. Some other customer used do the similar thing.

[albert_arquer]

Any thoughts?