Why the voltage of MISO between MC9S12DP256B and MC68CH908AZ60 is 2.5V?

[hitzhou]

Hi.

I have designed an ECU with MC9S12DP256B and MC68HC908AZ60 (maybe I should use
MC68HC908AZ60A). The two MCUs communicate via SPI.

The detail of the connection and voltage of the MISO could be seen in the attachment.

DP256B is in MASTER mode, while AZ60 is in SLAVE mode.

When the program runs, DP256B could transmit data to AZ60, but the received data of DP256B is wrong.

So I check the voltage of MISO and I fould that when transmitting data, the voltage of MISO is normal, that is 0V in low condition and 5V in high condition. But in idle condition, when the CLK is hold high, the vlotage of MISO is 2.5V.

Why?

What should I do to keep the communication between DP256B and AZ60 correctly?

How could I configure CPOL and CPOA or other register?

Thank you.

SPI.pdf

Message Edited by t.dowe on 2009-10-21 12:17 AM

[wade]

A quick thought (this has happened to me):
It may be that both devices are set to transmit, so the voltage you see results from contention of a '1' and a '0,' through your 33R resistor. Check the programming for slave and master
This could account for both the incorrect data and the incorrect voltage.

Wade Hassler

[bigmac]

Hello,

I suspect that what you are observing is the MOSI line becoming high-Z when the /SS signal to the slave is de-activated, and the voltage level drift under this condition.  To maintain correct logic levels whilst inactive, simply connect a pull-up resistor, say 10k, to the MOSI line.  You might also consider additional pull-ups on the MISO and SCLK lines should the master SPI ever be disabled.

However, your problems with return data from the slave are probably not due to this cause.  The CPOL and CPHA settings should be the same for each MCU.  Do you de-activate the /SS signal at the completion of each byte transfer, and then re-activate to commence the next byte?  This may be required, depending on your CPHA setting.

For the slave to correctly return a data byte, the value needs to be present in the SPI data register prior to /SS becoming active, and the commencement of clock pulses from the master.

Regards.

Mac