*address=value;
Message Edited by Alban on 2006-11-02 03:36 PM
I have the same problem. When performing the erase interlock write, I get a bus error. Any insight on why that would be? I am on an MPC5602P. I have verified through the code flash registers that the block is both unlocked and selected for erase. When I write to 0x0000000, I get a bus error. The freescale driver seems to have the same issue.
The erase sequence consists of the following sequence of events: 1. Change the value in the FLASH_MCR[ERS] bit from 0 to a 1. 2. Select the block, or blocks to be erased by writing ones to the appropriate registers in FLASH_LMSR or FLASH_HSR. NOTE: Lock and Select are independent. If a block is selected and locked, no erase will occur. 3. Write to any address in Flash. This is referred to as an erase interlock write. 4. Write a logic 1 to the FLASH_MCR[EHV] bit to start an internal erase sequence or skip to step 9 to terminate. 5. Wait until the FLASH_MCR[DONE] bit goes high. 6. Confirm FLASH_MCR[PEG] = 1. 7. Write a logic 0 to the FLASH_MCR[EHV] bit. 8. If more blocks are to be erased, return to step 2. 9. Write a logic 0 to the FLASH_MCR[ERS] bit to terminate the erase.
Does anybody solved the problem? and succed to write into flash?
Thanks
I use MPC555, and I've deselect CMF B FROM FLASH MEMORY by error (now i have only ???????? from 0x40000 to 0x6FFFF) . so I want to select this block to errase it. i found these steps but i don't know if that resolved the problem.
To set one or both of the bits in CENSOR[0:1],
1. Using section 19.7.6 A Technique to Determine SCLKR, CLKPE, and
CLKPM, write the pulse width timing control fields for an erase pulse, CSC = 1,
PE = 0 and SES = 1 in the CMFCTL register.
2. Write a one to the CENSOR bit(s) to be set.
3. Write EHV = 1 in the CMFCTL register. This will apply the programming voltages
to NVM bit 0 and the erase voltages to NVM bit 1 simultaneously.
4. Read the CMFCTL register until HVS = 0.
5. Write EHV = 0 in the CMFCTL register.
6. Read the CMFMCR CENSOR bit(s) that are being set. If any bit selected for set
is a 0 go to step 3.
7. Write SES = 0 and CSC = 0.
can someone help me to set CENSOR[0:1] to no censorship (01 or 10).
thanks for help
Hi ,
Just doing guesswork.
try to disable interrupt before erasing flash.
Let us know if it works or not.
Regards,
hi,
I can't do the example presented in 19.7.6 A Technique to Determine SCLKR, CLKPE, and
CLKPM, to clear or set censorship. MPC555 works at 10MHZ, and when set clock frequency more than 20 Mhz, the target goes to reset. so what are the values to be take for SCLKR, CLKPE, CLKPM ans PAWS to clear first Censor, then set it to no censor ship switch this procedure:
To clear CENSOR[0:1],
1. Write PROTECT[0:7] = 0x00 to enable the entire array for erasure.
2. Using section 19.7.6 A Technique to Determine SCLKR, CLKPE, and
CLKPM, write the pulse width timing control fields for an erase pulse,
BLOCK[0:7] = 0xFF, CSC = 1, PE = 1 and SES = 1 in the CMFCTL register.
3. Perform an erase interlock write.
4. Write EHV = 1 in the CMFCTL register. This will apply the erase voltages to the
entire CMF array and NVM bit 0 and the programming voltages to NVM bit 1
simultaneously.
5. Read the CMFCTL register until HVS = 0.
6. Write EHV = 0 in the CMFCTL register.
7. Read the entire CMF array and the shadow information words. If any bit equals
zero, go to step 4.
8. Read CENSOR[0:1]. If CENSOR[0:1] ≠ 0 go to step 4.
9. Write SES = 0 and CSC = 0.
trying to disable interrupt before erasing flash don't resolve the problem. have you more details please ?
thanks for help
You can look at some of the code at: