Brian Schimpf

XIRQ Timing

Discussion created by Brian Schimpf on Sep 10, 2006
Latest reply on Oct 26, 2006 by Alban Rampon
What is the minimum pulse width required to trigger an XIRQ interrupt request? I imagine that it has to be held low for one clock cycle, but I'm not sure. I'm using a 9S12DP256 processor specifically with the PLL active (3x multiplication).