Message Edited by Nabla69 on 2006-08-23 04:12 AM
Bit rate = 1M bit per secondBus length = 20mBus propagation delay = 5 x 10-9 sm-1
Step 1: Physical delay of bus = 20 x 5 x 10-9 = 100ns
Step 2: A prescaler value of 1 gives a CAN system clock of 8MHz and a Time Quantum of 125ns. This will give 1000 / 125 = 8 time quanta per bit.
Step 4: From 8 time quanta per bit, subtract 4 for PROP_SEG and 1 for SYNC_SEG. This leaves 3 which is the absolute minimum, so PHASE_SEG1 = 1 and PHASE_SEG2 = 2.
Step 5: RJW is the smaller of 4 and PHASE_SEG1, in this case 1
Step 6: From equation (10):
From equation (11):
The required oscillator tolerance is the smaller of these values, i.e. 0.0049 (0.49%) over a period of 12.75μs (12.75 bit periods). In this case the prescaler = 1 so no reduction in oscillator tolerance can be made without using a higher MCU oscillator frequency. Also PHASE_SEG1 =1 so only one sample per bit is possible.
In summary:Prescaler = 1Nominal Bit Time = 8PROP_SEG = 4PHASE_SEG1 = 1PHASE_SEG2 = 2RJW = 1Oscillator tolerance = 0.49%)
(Alban corrected copy/paste for legibility)
Message Edited by Alban on 2006-08-23 10:46 AM
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