#define PLL_TIMEOUT 50000#define PLL_LOCK_STATUS (CRGFLG_LOCK)#define PLL_CLEAR_FLAGS (CRGFLG = CRGFLG_RTIF_MASK | CRGFLG_PORF_MASK | \CRGFLG_LVRF_MASK | CRGFLG_LOCKIF_MASK | CRGFLG_SCMIF_MASK )/* Initializes the system clock in the CRG module */void Init_pll(void){uWord counter=0;/* Set PLL to give 40MHz from 16MHz Xtal *///Init multSYNR = 4;//Init DivREFDV = 1;//Enable auto tracking mode, turn on pll, clock monitor, self clock modePLLCTL = PLLCTL_AUTO_MASK | PLLCTL_PLLON_MASK | PLLCTL_CME_MASK | PLLCTL_SCME_MASK;//Wait for PLL lockwhile((PLL_LOCK_STATUS == 0) &&(counter < PLL_TIMEOUT)){counter++;}//Clear interrupt flagsPLL_CLEAR_FLAGS;//Enable loss of lock interrupt & self clock mode change interruptCRGINT = CRGINT_LOCKIE_MASK | CRGINT_SCMIE_MASK;if(PLL_LOCK_STATUS){//Enable PLLCLKSEL |= CLKSEL_PLLSEL_MASK; } ECLKCTL_NECLK = FALSE; //turn on ECLK output} /* end Init_pll *//*************************************************************************************/#pragma CODE_SEG __NEAR_SEG NON_BANKED /* these functions have to be allocated in the non banked area */INTERRUPT void PLL_Lock_ISR(void){/* try to restart pll */Init_pll();_asm("bgnd");} /* end CPU12PLLLockISR */INTERRUPT void PLL_SCM_ISR(void){uWord i;/* wait here while in self clock mode */while(CRGFLG_SCM){_asm("bgnd");/* flash both red and green LED to indicate a severe problem */for(i = 0; i < 60000; i++);if(IS_PIN_HIGH( LED_PORT, RED_LED_PIN)){SET_PIN_LOW(LED_PORT, RED_LED_PIN);SET_PIN_LOW(LED_PORT, GREEN_LED_PIN);}else{SET_PIN_HIGH(LED_PORT, RED_LED_PIN);SET_PIN_LOW(LED_PORT, GREEN_LED_PIN);}} /* try to restart pll */Init_pll();} /* end CPU12PLLLockISR */#pragma CODE_SEG DEFAULT /* switch back to default segment */
Message Edited by Alban on 2006-08-10 08:16 AM
We have a 16MHz loop controlled Pierce with 33pF on both XTAL and EXTAL to ground. The PLL filter has a 4.7K resistor and 1500pF series cap with a 100pF parallel cap. Is the full swing Pierce more robust? My hardware guy is reviewing things like conformal coating, PCB layout and component selection. It is somewhat disconcerting to know that the PLL loss of lock is "normal". But lets assume that we have to live with it.
My question was on the software not the hardware. Assuming that it is possible to loose the PLL lock, I need to determine if this mode can be recovered in time to not cause catastrophic effects on our control system (50-100uS) or if I just need to immediately go into fail safe mode. In the case of the self clock mode, I would like to use the self clock mode ISR to force the system into fail safe and then reset before our external watchdog times out. Could you please comment on the register settings required to do that and why my test code SCM ISR doesn't execute?
-Dan