Eric Peterson

PLL Question

Discussion created by Eric Peterson on Apr 11, 2006
Latest reply on Jan 12, 2011 by Mohammad Shekarforoush
I am using the MC9S12DP256B microcontroller and I have written a routine to utilize the phase loop lock feature. Every time I run the debugger in codewarrior my program goes into the clock monitor fail reset.

The code that I have written is as follows:

void SetClkSpeed20(void)
{
//multiply 4MHz by 2 by 5/1 to get 40MHz for the PLL
//or a bus clk of 20 MHz
SYNR=4;//+1
REFDV=0;//+1
while (!(CRGFLG_LOCK)) ;//wait for PLL lock
CLKSEL_PLLSEL=1; //engage PLL
}

I am also using SPI in this program, is there an issue with using both SPI and PLL that would cause the clock monitor fail reset or could I be missing something in my PLL routine that is causing the clock monitor fail reset. Any advice or insight into this interrupt or problem would be appreciated.

Thanks,
Lssuer

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