So I'm confused. I found this thread which only confirms my confusion. I'm using a 9S08QE32 (though this question applies to quite a few chips in the S08 family.
Page 21-22 of the QE32 reference manual states:
ICSOUT — This clock source is used as the CPU clock and is divided by two to generate the
peripheral bus clock, BUSCLK.
I have the FLL selected as my ICS, so therefore my rate is 8.372 MHz. Further, my BUSCLK would be 4.186 MHz, right?
For my SCI port, page 222-223 says the BAUD is calculated with:
BAUD = BUSCLK / (SBR[12:0] * 16)
Or written a different way:
SBR = BUSCLK / (16 * BAUD)
But my baud calculations are off. It's as if the BUSCLK is off by that factor of two. If I set my BAUD to 9600, the serial port actually is working at 19200. 2x error.
What am I missing here?
Hello irob,
The formulae for calculating the bus frequency were derived from data given at a number of locations within the Reference Manual. The primary reference is Tables 11.6 and 11.7 that indicate a number of different DCO ranges, and the FLL factor associated with each range. The low and mid ranges would be mostly of interest. It is appropriate for the internal reference use, that ICSSC_DMX32 = 0.
From Table 11.7, you can deduce that
DCO_freq = fref * FLL_factor
Then from Fig. 11.2 block diagram it can be observed that, when FLL output is selected,
ICSOUT_freq = DCO_freq / Bdiv
where Bdiv = 1, 2, 4 or 8, determined by ICSC2_BDIV setting
Further reference to section 1.3 and Fig. 1.2, show a further divide by 2 stage, so that
BUSCLK = ICSOUT_freq / 2
Combining these expressions will result in the previous formulae. For yur current register settings that use low range by default, the FLL factor will be 512, and Bdiv is 1, giving
BUSCLK = fref * 512 / 1 / 2 = fref * 256
Since fref will be trimmed somewhere within the range 31.25 to 39.0625 kHz, the bus frequency will have the range 8.000 MHz to 10.000 MHz, double the frequency that you were anticipating. If you were to trim the reference frequency for 32.703 kHz, as was previously implied, the actual bus frequency would be 8.372 MHz. For 9600 bits per second, the SBR setting would need to be 54 or 55, for a baud error of about 1 percent.
With the code lines,
ICSSC_IREFST = 0; // source of reference clock is external clock.
ICSSC_CLKST = 0b00; // output of FLL is selected
these will not do anything since you are attempting to write to read-only status bits. However, you should explicitly set the DRS and DMX32 bits, rather than relying on the POR default. ICSSC = 0; would be more appropriate for ICS initialisation.
Regards,
Mac