Hi,
I am trying to implement the following CAN bit timing specification on TWRS12G240 which has a MC9S12G240 microcontroller, the tower is using TI SN65HVD1040 transceiver.
Parameter | Value |
Baudrate | 500 kBaud ± 0.1% |
Bit Time | 2 μs |
Number of Time Quanta per Bit-time | 16 |
SJW (Time Quanta)* | 3 |
SAMPLE Point (% of Bit Time)* | 75% |
Sampling mode | Single |
Resynchronization | recessive to dominant |
Bus length
The maximum bus length allowed is 20 meters. Twisted wires shall be used for the CAN bus
and the maximum specific line delay of the wire shall be 5 ns/m.
Transceiver Delay
Maximum allowed transceiver loop delay (Tx to Rx delay) for both dominant bit to recessive bit
and recessive bit to dominant bit is 300ns
Oscillator Tolerance
The maximum allowed oscillator tolerance of CAN source clock is ± 0.1%.
I am using PLL as can bus clock and pll is being generated thorugh on board 8 Mhz crystal. If I input 32 Mhz as CAN bus clock then every parameter is matched except oscillator tolerance which comes out to be 1.21%. Now my question, can the above bit timing parameters can be realized with different bus clock value because I am unable to come up with any combination of prescaler and bit time and time quanta. Since bit time and time quanta per bit time is fixed there is little left that could be done.
According to my calculations
Prescaler comes out as 4
Tq = 32Mhz/4= 8 Mhz= 125ns.
Prop delay of bus= 20 * 5/1000000000=100ns
prop_seg= 2 *( propagation delay of transciever+ prop delay of bus)=2(230+100)=660
=660/125=5.28=5
phase_seg1=5
Phase_seg2=5
RJW =4
delta f=4/20*10=0.0125
delta f <min(phase_Seg1,phase_seg2)/2(13*NBT-phase_seg2)
=5/2*(13*16-5)=0.0123=1.23%
CAN is somwhat picky with bit bit timing. Generally, they said in the first CAN drafts that an oscillator tolerance of 1.58% was the worst case, so I you should aim to get below that at least (I'm not sure what the ISO 11898 says). If your application relies and revolves around CAN, you should consider picking an oscillator based on the CAN baudrates you want to use. Though note that if you fiddle around with the number of tq/bit and the SJW, you might get a more accurate location of the sample point.
As for the spec on where to place the sample point etc, I would strongly recommend to follow the CANopen standard DS301, chapter 5.4. I believe you can download the standard for free if you register at CAN-In-Automation, www.can-cia.de. .The bit timing there is pretty much industry standard for all CAN applications. Don't follow timing specs from Freescale manuals/app notes, they are pretty obscure and non-standard. Avoid them in particular if you are implementing any of the mainstream CAN protocols like CANopen, DeviceNet or J1939.
For convenience, this is what DS301 says about 500kbps:
Valid range for location of sample point: 85% to 90%
Recommended location of sample point: 87.5%
Estimated bus length (based on sample point recommendations): 100m.
In my projects with 8MHz-ish oscillators, for MSCAN and FlexCAN both, I use the following ideal setup for 500kbps with 87,5% sample point:
16tq where:
1=sync,
13=pre sample,
2=post sample,
SJW=2.