Satinder Sekhon

Setting CAN Bit Timing parameters

Discussion created by Satinder Sekhon on Aug 24, 2012
Latest reply on Feb 26, 2013 by Grzegorz Konopko

Hi,

 

I am trying to implement the following CAN bit timing specification on TWRS12G240 which has a MC9S12G240 microcontroller, the tower is using TI SN65HVD1040 transceiver.

 

Parameter

Value

Baudrate

500 kBaud ± 0.1%

Bit Time

2 μs

Number of Time Quanta per Bit-time

16

SJW (Time Quanta)*

3

SAMPLE Point (% of Bit Time)*

75%

Sampling mode

Single

Resynchronization

recessive to dominant

 

Bus length

The maximum bus length allowed is 20 meters. Twisted wires shall be used for the CAN bus

and the maximum specific line delay of the wire shall be 5 ns/m.

Transceiver Delay

Maximum allowed transceiver loop delay (Tx to Rx delay) for both dominant bit to recessive bit

and recessive bit to dominant bit is 300ns

Oscillator Tolerance

The maximum allowed oscillator tolerance of CAN source clock is ± 0.1%.

 

I am using PLL as can bus clock and pll is being generated thorugh on board 8 Mhz crystal. If I input 32 Mhz as CAN bus clock then every parameter is matched except oscillator tolerance which comes out to be 1.21%. Now my question, can the above bit timing parameters can be realized with different bus clock value because  I am unable to come up with any combination of prescaler and bit time and time quanta. Since bit time and time quanta per bit time is fixed there is little left that could be done.

 

According to my calculations

 

Prescaler comes out as 4

Tq =  32Mhz/4= 8 Mhz= 125ns.

Prop delay of bus= 20 * 5/1000000000=100ns

prop_seg= 2 *( propagation delay of transciever+ prop delay of bus)=2(230+100)=660

=660/125=5.28=5

phase_seg1=5

Phase_seg2=5

RJW =4

delta f=4/20*10=0.0125

delta f <min(phase_Seg1,phase_seg2)/2(13*NBT-phase_seg2)

=5/2*(13*16-5)=0.0123=1.23%

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