Need help to configure PIT timer

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Need help to configure PIT timer

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Mamat
Contributor I

Hello!

I am new in embedded systems and I try to configure my PIT timer but have some problems.

I work on TWR-K60N512 and I would like to raise an interrupt each 0.5 sec thanks to my timer.

In debug mode I stop correctly on my breakpoints in the function isr_PIT2 (which manage the interrupt).

But when I run my code in normal mode, it doesn't seem to be working.

This is what I did already : 

 

void main(void)
{


disable_watchdog();

// Enable clock for port A
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;

//Set PTA10 (connected to LED's) for GPIO functionality
PORTA_PCR10 = (0|PORT_PCR_MUX(1));

//Change PTA10 in output mode
GPIOA_PDDR = GPIO_PDDR_PDD(GPIO_PIN(10));

//Enable external clock (50mhz)
OSC_CR |= OSC_CR_ERCLKEN_MASK;

//Select system oscillator for MCGCLKSEL
SIM_SOPT2 &= ~SIM_SOPT2_MCGCLKSEL_MASK;


//
MCG_C1 |= MCG_C1_CLKS(0x2);

//Divide frequency by 10 on OUTDIV2 (bus clock)
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV2(0xA);

//*************************** PIT *************************************

//Activate PIT clock in SIM_SCGC6
SIM_SCGC6 |= SIM_SCGC6_PIT_MASK;

//Turn on PIT timer

PIT_MCR &= ~PIT_MCR_MDIS_MASK;


//Timer will stop in debug mode
PIT_MCR |= PIT_MCR_FRZ_MASK;


// Timer 2
PIT_LDVAL2 = 0x26259F; //2 500 000 - 1


// TIF = Time Interrupt flag. Is cleared by writing it with 1.
PIT_TFLG2 = PIT_TFLG_TIF_MASK;


NVICIP70 = 0x30; //Set priority 3 
NVICICPR2|=(1<<6);//Clear any pending interrupts
NVICISER2|=(1<<6);//Enable interrupts


PIT_TCTRL2 = PIT_TCTRL_TIE_MASK;
PIT_TCTRL2 |= PIT_TCTRL_TEN_MASK;




while(1)
{


}


}


void disable_watchdog()
{
asm(" CPSID i");
/* Write 0xC520 to the unlock register */
WDOG_UNLOCK = 0xC520;
/* Followed by 0xD928 to complete the unlock */
WDOG_UNLOCK = 0xD928;
/* enable all interrupts */
asm(" CPSIE i");
/* Clear the WDOGEN bit to disable the watchdog */
WDOG_STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK;
}

 

//********************************Interrupt code************************

 

(tIsrFunc)isr_PIT2,

 

void isr_PIT2(void)
{
PIT_TFLG2 = 0x01;

//Toggle blue LED on each interrupt
GPIOA_PTOR|=GPIO_PDOR_PDO(GPIO_PIN(10));
}


 

Thanks for your help

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1 Solution
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ndavies
Contributor V

Wrong errata sheet. That is the Errata sheet for the system board. It doesn't cover the specific MCU soldered onto the board. You need to look at the Errata for the specific K60 mask of the chip you have on the K60 board.

Different Masks of the K60 chips have differrrent Errata.

 

I am also using the K60N512 tower board. It has A Kineits PK60N512Vmd100 chip with the mask of 0M33Z. So the Errata sheet was

http://cache.freescale.com/files/microcontrollers/doc/errata/KINETIS_0M33Z.pdf?fpsp=1&WT_TYPE=1Errat...

 

And the actual errata text Reads:

e2682:   PIT: Does not generate a subsequent interrupt after clearing the interrupt flag Errata type:   Errata Description:  The PIT does not generate a subsequent interrupt after clearing the interrupt flag in the ISR upon receiving the first interrupt. Thus, the second interrupt will never be triggered. Mask Set Errata for Mask 0M33Z, Rev. 28 MAR 2012 Freescale Semiconductor, Inc. 17Workaround: In order to enable the use of subsequent interrupts from the PIT, the user must access any PIT register after clearing the interrupt flag in the ISR.

 

(Sure sounds like your issue)

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Mamat
Contributor I

I forgot to say that my frequency in the PIT timer is 5Mhz (if my configuration is good)

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ndavies
Contributor V

Check the errata list for the part you are using. There is a PIT errata on some of the masks. On some parts you need to read a PIT register after you clear the interrupt flag otherwise the interrupt does not reenable.

 

If you were viewing the PIT registers in the debugger, Your Debugger did this for you while you were stepping through the code.

 

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Mamat
Contributor I

Thanks for your reply

However I kooked into the errata but there is nothing concerning the PIT timers

(http://cache.freescale.com/files/microcontrollers/doc/errata/TWRK60N512HWER.pdf?fpsp=1)

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2,045 Views
ndavies
Contributor V

Wrong errata sheet. That is the Errata sheet for the system board. It doesn't cover the specific MCU soldered onto the board. You need to look at the Errata for the specific K60 mask of the chip you have on the K60 board.

Different Masks of the K60 chips have differrrent Errata.

 

I am also using the K60N512 tower board. It has A Kineits PK60N512Vmd100 chip with the mask of 0M33Z. So the Errata sheet was

http://cache.freescale.com/files/microcontrollers/doc/errata/KINETIS_0M33Z.pdf?fpsp=1&WT_TYPE=1Errat...

 

And the actual errata text Reads:

e2682:   PIT: Does not generate a subsequent interrupt after clearing the interrupt flag Errata type:   Errata Description:  The PIT does not generate a subsequent interrupt after clearing the interrupt flag in the ISR upon receiving the first interrupt. Thus, the second interrupt will never be triggered. Mask Set Errata for Mask 0M33Z, Rev. 28 MAR 2012 Freescale Semiconductor, Inc. 17Workaround: In order to enable the use of subsequent interrupts from the PIT, the user must access any PIT register after clearing the interrupt flag in the ISR.

 

(Sure sounds like your issue)

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Mamat
Contributor I

Thanks ndavies!

Your post will probably help me a lot.

I am at school right now but I will test this solution tonight.

I will tell you if it works, thanks!

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2,044 Views
Mamat
Contributor I

It works!

You can't imagine how you helped me ndavies..

I have been trying to solve this problem for months.. I never found this document before.

Thanks a lot!

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