Kirk Humphries

SRAM memory in 9s12xdp512 QFP-144

Discussion created by Kirk Humphries Employee on Jan 28, 2006

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Posted: Mon Oct 10, 2005  10:25 am

 

Dear Friends,

 

We have to desing a new application with the new 9s12xdp512 , in expanded more, with external SRAM memory.

 

Anyone has some expirience with this microcontroller with SRAM memory?

 

In freescale AN 2708 there is and introduction to the external bus for those mcu's, but any real example is inside.

 

Thanks in advance!

 


 

Date: Mon Oct 10, 2005  11:34 am

 

I have experience with Normal expanded mode design for the MC9S12XDP512, and it is very simple.

 

I used a 256K * 16 SRAM (Cypress CY7C1041B or Samsung K6R4016C1D in my case).

 

The connections are as follows:

- RAM A[17:0] to S12X A[18:1] (Ports K, A and B)

- RAM D[15:0] to S12X D[15:0] (Ports C and D)

- RAM CS to one of the S12X CS3 - CS0 lines (Port J)

- RAM OE to S12X RE (PortE5)

- RAM WE to S12X WE (PortE2)

- RAM UB to S12X UDS (PortB0)

- RAM LB to S12X LDS (PortE3)

 

As you can see the above connection involves no glue-logic (no logic gates, just the S12X and the SRAM device). The maximum speed is achieved in this connection - which is 1 wait-state (the minimum in Normal Expanded mode). I have tested it to run to 25MHz external RAM bus-rate, when the internal S12X bus functions at 50MHz bus speed.

 

(In Emulation modes it is possible to operate external RAM with no wait-states at all, but there is a lot of glue-logic that is required in this mode. Emulation modes are intended primarily for emulator-makers and so we are using Emulation modes in our S12X full-emulator)

 


 

Date: Tue Oct 11, 2005  4:16 pm

 

Thank you very much for your help!!! It is really apreciaded for us.

 

Well we are going to make a little prototype board with some SRAM memoy and we are going to connect it to the HCS12X mcu like you told us. Without logic gates, .. It is fantastic in that mcu.

 

We have experiencie with the 9s12dp256 mcu and sram, and it is horrible. A lot of timing problems, voltage levels, etc.

 

We are going to move to this new mcu because we need speed and external memory in our application, we have to work with a lcd too.

 

We have read you article "A Guide for Motorola HCS12 Expanded Mode Bus-Design" and it was very instructive for us.

 

I have some questions:

 

1.- You have choosed the K6R4016C1D ASYNC FAST SRAM, from Samsung, can we use the Samsung SRAM family Low Power SRAM, like K6X8016C3B,512Kx16,4.5V~5.5V,55ns or 70ns to increase the SRAM size?

 

2.- Do you know is SRAM memory often to have WAIT# output signal?

 

3.- What are the more important parameters of SRAM that I have to check to choose the properly SRAM memory?

 

We have read your document "A Guide for Motorola HCS12 Expanded Mode Bus-Design", and it was really instructive for us. We have worked with 9s12dp256 mcu in expanded mode and we have been several problems like timing problems, levels problems, etc. Nice document, congratulations for it!!

 

Thanks again for your cooperation.

 


 

Date: Tue Oct 11, 2005  6:46 pm

 

I am glad you liked the HCS12 Expanded Mode Design Guide I wrote.

 

You are right that the HCS12 Expanded Mode Design is very difficult.

 

You are also right that the S12X is much much better for expanded mode designs when used in Normal-Expanded mode. The S12X has very good external-bus timing, good voltage levels to allow nice interfacing to SRAMs with TTL voltage levels, are requires no glue logic to external SRAM.

 

>1.- You have choosed the K6R4016C1D ASYNC FAST SRAM, from Samsung, Can

>we use the Samsung SRAM family Low Power SRAM, like

>K6X8016C3B,512Kx16,4.5V~5.5V,55ns or 70ns to increase the SRAM size?

 

I looked at the data sheets of the K6X8016C3B and it looks like it will work just fine for you. You just need to make sure you initialize the right number of wait-states as appropriate for the access time of the SRAM you are using. Assuming you will set the internal S12X bus speed to 40MHz, you can set the following number of wait-states:

 

For a 55nSEC SRAM initialize for 2 wait-states.

For a 70nSEC SRAM initialize for 3 wait-states.

 

You initialize these in the EBICTL1 register at address 0x000F. (Make sure you use the newer mask-set 0L15Y and not 0L40V)

 

>2.- Do you know is SRAM memory often to have WAIT# output signal?

 

No, I don't know any SRAM that generates a WAIT output. If you want to drive the S12X EWAIT signal, I think you will need to use some external logic to generate this signal. You may need that if you use a very-slow LCD, that requires more than 8 S12X Wait-states.

 

Currently, the S12X has one setting of Wait-States (in the EBICTL1 register) for the entire external address range. On a future S12X device that will be introduced in 2006, there will be provision to set up two different wait-states settings for different chip-selects.

 

> 3.- What are the more important parameters of SRAM that I have to

> check to choose the properly SRAM memory?

 

The best SRAMs that work with the S12X are the 16-bit wide asynchronous SRAMs. These RAMs can work with the S12X with no glue logic (just the SRAM and the S12X).

Other than that, the S12X bus is very accommodating, so you can chose just about any SRAM, and it will work as is. Note also that the S12X may be operated at either 3.3V or 5V, so by supplying 3.3V to the S12X you may use a 3.3V SRAM.

 


 

Date: Fri Oct 14, 2005  4:32 pm

 

We are going to test the 9s12xdp512 LQFP-144 MCU next with the same memory that you have used, the K6R4016 I will give you some news about how is goig the test.

 

Regarding this new HCS12X family, just I can say that they seem a powerful chip, but they handicap for It is thay is too NEW, our Dealer say us that the chip will in on mass production in 2006 (January), and

 

Is a little dificult to find chips to make prototypes. Another handicap is that there is not Process Expert from CodeWarrior, this tool is very helpful to save time, isn't it?

 

I have to prepare a new prototype card and I need for to make the board the package file for LQFP 144-Pin for Layour (Cadence or Orcad), do you have this symbol?

 

We are going to test the chip with SOFTEC Starter Kit next week,

 

http://www.softecmicro.com/products.html?type=detail&title=SK-S12XDP512-A

 

Have you see it before this EBV?

 

Well, it's time to finish to work.

 

Thanks for help us.

 


 

Date: Sun Oct 16, 2005  7:20 am

 

Maybe you can try to order some samples for your prototype on the Freescale web-site. I heard some good things about this web-site sample-order system in recent months. In any case once you get the samples I think you will appreciate you are using the S12X rather than the HCS12 for your expanded mode application, as the S12X is really much better to connect to external memory.

 

Regarding the layout, I am renting Power-PCB for my layouts, so I don't have the LQFP 144 pin footprint in Orcad or Cadence.

 

Regarding the EVB, I don't have experience with the specific EVB you are considering. I was using the Freescale S12X EVB from my early evaluation, and for our BDM work.

 

I am working for Nohau, and develop full-emulators and BDM for the debugging of the S12X, HCS12 and HC12 families. These are high-end debugging tools to allow shortening the design cycle by providing ways to find bugs quickly (typically save several months off a typical design cycle). The full-emulator can additionally be used as a replacement for an EVB, as it is equipped with an MC9S12XDP512 cpu, and can run either stand alone to start testing your code before you have a target, or attached to a target board once you do have your own target. If these Nohau tools are of interest to you, you can contact me off-list and I will be happy to give you more detailed information.

 

Good luck and best regards,

 


 

Date: Thu Oct 20, 2005  11:26 am

 

We have finished a simple SRAM prototype with the K6R4016C1D Samsung memory, and now We have one software engineer trying to test this prototype with the 9s12xdp512fv mcu and codewarior compiler.

 

Do you have a simple project example from codarrior for to test the SRAM? is only to see the register setup and instructions.

 

Thanks in advance for your nice help.

 

Best Regards,

 


 

Date: Thu Oct 20, 2005  1:07 pm

 

I have the settings in assembly level. (The actual code was written in assembly, using the Cosmic S12X compiler).

 

Here are the settings:

 

; Set the ModeReg to Normal Expanded Mode

movb #$A0, ModeReg

 

; For the case that this program executes while emulating

; Expanded Mode initialize the external bus to 1 wait-state

; (the minimum possible wait-states on the target bus

; in expanded mode), and initialize all 4 Chip-Select

; signals to be active, to allow accesses to the target memory.

; (the Flash emulation memory still uses 0 wait-state,

; and so does the internal S12X RAM)

 

movb #$0F, MmcCtl0_Reg ; Enable CS0, CS1, CS2 and CS3

movb #$00, EbiCtl1_Reg

 

then, the access of the external RAM is done by setting the GPAGE register to appropriate page value, and using the GLD and GST instruction to load or store values to the external RAM.

 

Depending on which CS signal you connected to your external RAM (CS1, CS2, CS2 or CS3), you could also access your external RAM through the RPAGE or the EPAGE register. Through the RPAGE register, the access will be for example:

 

MOVB #$01, RPageReg

INCW $1000

 

to increment the value of a word in your external RAM.

 

The advantage of using the RPAGE or EPAGE windows is that then the compiler has much more instructions to act directly on the external RAM content to manipulate it, where if you are limited to using the GPAGE register only, you can only use the GLD and GST instructions, so then whenever you need to manipulate an external RAM value the compiler first need to bring the variable internally using the GLD instruction, then manipulate it in one of the internal CPU registers, then store it back externally using the GST instruction.

 

Hope this helps,

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