Kirk Humphries

DEMO9S12XDT512 oscilator (Part 1)

Discussion created by Kirk Humphries Employee on Jan 26, 2006
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Posted: Tue Jan 10, 2006  11:38 am
 
Hi,

Are there oscilators having 0-2.5V output while powered from 5VDC source? And oscilator socket on this board is wired directly to 5VDC and via clock select jumper to EXTAL but absolute max for voltage on EXTAL is 3V... Yes, I now how to enable PLL but I just want faster oscilator clock.

Posted: Tue Jan 10, 2006  6:51 am

To the best of my knowledge there are no oscillators that are powered by 5V and output 0 - 2.5V clock output.

At low clock frequency, some designs are using a 5V clock oscillator with two equal resistors to form a voltage divider on the oscillator output, so the EXTAL pin gets the divided voltage of 0 - 2.5V. This works only in low frequencies however. In high frequencies, the RC delay formed by the resistors and the parasitic capacitance on the EXTAL input makes such voltage divider marginal in its operation and impractical.

At high frequencies, we used a translation buffer that is powered by an external 2.5V supply to bring down the voltage levels from the 0 - 5V range to the 0 - 2.5V range.

Hope this helps,

Posted: Tue Jan 10, 2006  7:18 am

Thanks

I also haven't heared about such oscilators. Looks like guys at Axiom overlooked specs a bit or forgot to add 5V->2.5V translation stage. I guess XDT512 in this board could survive 5V oscilator for some time but I'll better fix it or use only crystal for now.

Darren, I agree that this board should be fixed, either using 2.5V regulator to power 3V oscilator, or adding 5V->2.5V translator before clock select jumper.

Posted: Tue Jan 10, 2006 11:13am

I heard people use a simple voltage divider (two resistors).

Posted: Tue Jan 10, 2006 8:25pm

Yes, I used 2 of 1K resistors in series to create the 2.5V swing to clock a 9S12XDP512. It works well enough.

Posted: Tue Jan 10, 2006 8:49pm

I was curious about this:

When driving such divider divider with ideal outputs, the impedance driving the input capacitance high is 1000R (the impedance when driven low is 500R). The input capacitance on an XDP256 is quoted as 7pF. This gives a rise time of 7nS and a fall time of 3.5nS with not other parasitics. This is well outside the 1nS quoted as maximum recommended rise time. It may well work, but if you are the least bit retentive about your designs.

Interestingly the DP256 EVB uses a 16MHz oscillator run at 5V. In this case the divider consists of 12K//22pF in series with 1K to ground. 22pF at 16MHz has an impedance of 452ohms - in parallel with 12K is 435R. This is gives 3.1nS (if you take the capacitance as a pure resistance which it isn't). Since this is Freescale's solution, maybe it is a better answer than two resistors.

 


 

Posted: Wed Jan 11, 2006 1:26 PM

>
> I heard people use a simple voltage divider (two resistors).
>


Yes, I used 2 of 1K resistors in series to create the 2.5V swing to clock a 9S12XDP512. It works well enough.

 

 

 

Posted: Wed Jan 11, 2006 8:37am

There's no meaning to calculating the cap's impedance at the clock frequency. It (and the capacitance of the micro's input and stray capacitance) are most critical during clock transitions. The voltage divider is more like 22pf driving the input and stray capacitances to ground.

For slow clocks (but who would go slow, anyway?), this combo would develop negative voltages at the clock input. The steady-state voltage is around .4V (12k driving 1k) so during high state the cap charges to 4.6V. Low-going transition then tries to drive the input to -4.6V.

Also: Why is 1k/1k divider not 500 ohms both directions?

 

 

Posted: Wed Jan 11, 2006 9:35am

> There's no meaning to calculating the cap's impedance at the clock
> frequency. It (and the capacitance of the micro's input and stray
> capacitance) are most critical during clock transitions. The

Also I thought there was no way to determine risetime with characteristics of input (resistor and MCU capacitance) but no mention of characteristics of the oscillator which drives it.

> For slow clocks (but who would go slow, anyway?), this combo would
> develop negative voltages at the clock input.

I thought contrary... Why go fast when you can go slower and use the PLL? Which is better when considering harmonics interference?

 

Posted: Wed Jan 11, 2006 10:20am

> Also: Why is 1k/1k divider not 500 ohms both directions?

Yes one could use 500 Ohms.

Mainly current draw. I tried Freescale recommendation (I didn't like the scoped signal), 10K is problematic, 1K and 470 Ohms. I settled for 1K. For me it works enough, I didn't try to overly analyze clock specs.

Posted: Wed Jan 11, 2006 0:27pm

> I thought conrary... Why go fast when you can go slower and use the
> PLL? Which is better when considdering harmonics interference?

4*4MHz PLL is not equivalent to 16MHz OSC clock at least for 2 reasons:

1) What about PLL jitter and CAN @ 1Mbps? Should be OK but with higher osc just -1 thing to care about.

2) Slower part programming. At least you should convince your pragrammer/debugger that you have PLL filter attached and that it's OK to go faster.

Posted: Thu Jan 12, 2006 1:58am

[PLL?]

> 4*4MHz PLL is not equivalent to 16MHz OSC clock at least for 2 reasons:
>
> 1) What about PLL jitter and CAN @ 1Mbps? Should be OK but with higher

Look at the PLL jitter specs and tell me where the problem is - I didn't find any.

A very good reason to use the PLL is that it isolates the CPU clock from the clock input (against transients).

BTW: Both pierce and colpitts configurations are rock solid when designed properly, especially at lower frequencies (8MHz and below). Therefore a canned oscillator is suitable only for very low production volume.

> 2) Slower part programming. At least you should convince your
> pragrammer/debugger that you have PLL filter attached and that it's OK to go
> faster.

Ack, some BDM tools don't support PLL. So don't use a too low oscillator frequency.

Posted: Thu Jan 12, 2006 9:59am

> Look at the PLL jitter specs and tell me where the problem is - I
> didn't find any.

The specs does not tell all. In my case where I used the byteflight in the 9S12DB128 with PLL. The byte flight was useless when using a PLL at full speed, jitter was too much so I have to use can oscillator, more stable.

 

Continued in DEMO9S12XDT512 oscilator (Part 2)

Message Edited by khumphri on 01-26-2006 11:00 AM

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