i.MX RT can support 2 hyper flash ?

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i.MX RT can support 2 hyper flash ?

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Contributor II

hyper flash can't be write or read if it is configured as boot device via flexspi.

My customer need extra hyper flash for data storage others than boot hyper flash.

I look the spec, i.MX RT can support 2 hyper flash via flexspi.

If one is configured as a boot device, can I use the other one for data storage or someone else usage.

12 Replies

174 Views
Contributor II

This example is run from SRAM or SDRAM directly.

It doens't show how to copy boot image from hyper flash or QSPI Flash to SRAM/SDRAM like "Plain load image"

I read the other question in the forum.

"Plain load image" is only for LPC540xx and not for i.MX RT.

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174 Views
Contributor I
Is it possible to read and write on another norflash? Here's the situation: portA put the program, xip mode; Another norflash(portB) puts the data, but it doesn't work.
Is it because flexspi shares a bus??
Is it solved now?thank u.
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174 Views
NXP TechSupport
NXP TechSupport

yes, read and write on another norflash is possible.

Best regards
igor

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NXP TechSupport
NXP TechSupport

unfortunately I an not familiar with LPC processors and "Plain load image".

Suggest to look at app notes describing qspi booting process on:

i.MX RT1050 MCU/Applications Crossover Processor | Arm® Cortex®-M7 @600 MHz, 512KB SRAM |NXP 

In general qspi/hyperflash boot image is the same image which will be executed from sdram with addition of header.

Header is described in sect.2.5. Boot Image AN12107. There are special tools (sect.3. Program tools) which use

complicated procedures for generating header and whole image. If your question is about how to generate boot image

without using these tools, just running some sdram application for generating new boot image and writing it to qspi,

I belielve such complex task is not supported in nxp software.

Best regards
igor

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174 Views
NXP TechSupport
NXP TechSupport

HI Li

right, from sect.30.2 Introduction i.MX RT1050 Reference Manual :
FlexSPI is a flexible SPI (Serial Peripheral Interface) host controller which supports two
SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/
Octal mode data transfer (1/2/4/8 bidirectional data lines).

It can be used as boot device for one and the other for data storage or something else.

Best regards
igor
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174 Views
Contributor I

Hi igorpadykov,

If the processor is running in XIP mode using the FlexSPI interface, can it use the same interface to access the other devices?

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174 Views
NXP TechSupport
NXP TechSupport

yes this is possible

Best regards
igor

174 Views
Contributor II

If I can copy all boot image into SRAM/SDRAM, is that possible to erase/write free space in the boot hyper flash.

If yes, what's detail? is that example how to do it.

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NXP TechSupport
NXP TechSupport

if processor runs from SRAM/SDRAM it can erase/write hyper flash,

please check MCUXpresso examples.

Welcome | MCUXpresso SDK Builder 

~igor

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174 Views
Contributor II

Which example  I can reference?

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NXP TechSupport
NXP TechSupport

  SDK_EVKB-IMXRT1050/boards/evkbimxrt1050/driver_examples/flexspi

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174 Views
Contributor I

Hi igorpadykov,

In the MIMXRT1050 EVK booting from Hyper-Flash and running in XIP mode.

Could I access the QSPI-Flash and how to do this?

Sincerely,

Larry

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