The manual states in section 184.108.40.206 Gated Clock Mode:
The CSI can be programmed to support rising/falling-edge
triggered VSYNC through CSI_CR1[SOF_POL]
However, when I set SOF_POL=1 this has no effect. CSI still triggers on rising edge.
I'm using traditional interface, CCIR_EN=0, CCIR_MODE=0, EXT_VSYNC=0.
Question: How can VSYNC be configured for falling edge?
Thanks for your reply.
Let me rephrase the question: I do apply an external signal to VSYNC and notice that the DMA starts on the rising edge. My external circuitry requires that DMA starts on the falling edge. How can I achieve that?