RT1050 LWIP flash启动，变量在SDRAM区域

[haifeng_jin]

hi  使用的SDK是2.5.0，LWIP历程修改，采用qspi flash启动，但是把ram变量定义到SDRAM中，下载代码，跑起来了，但是ping过去只能发送，ping不通网关，整个硬件电路完好，如果换成sdram 仿真的历程，没有问题，不知道问题出在哪里，下面是我的scf文件：

#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/

#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000

#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000

#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400

#define m_text_start 0x60002400
#define m_text_size 0x03FFDC00

#define m_data_start 0x80000000
#define m_data_size 0x01E00000

#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000

//#define m_data_start 0x20000000
//#define m_data_size 0x00020000

#define m_data2_start 0x20000000
#define m_data2_size 0x00020000

#define m_data3_start 0x20200000
#define m_data3_size 0x00040000

/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x1000
#endif

#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x1000
#endif

#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (.boot_hdr.conf, +FIRST)
}

RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
}
#else
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
#endif
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
*(m_usb_dma_init_data)
*(m_usb_dma_noninit_data)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
}

[jeremyzhou]

Hi haifeng jin,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Please add the macro: XIP_BOOT_HEADER_DCD_ENABLE=1 in the Define box (Fig 1), then try again.

Have a great day,
TIC

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