RAM utilization in RT1172

[AndreiZi]

Hello,

I am trying to utilize different areas of RAM memory in RT1172.

So, I defined the next (similar to EVK):

See in attached pictures

I have one array in code:

uint32_t image_data1[100][100];

Resulting in next memory map:

Memory region Used Size Region Size %age Used

BOARD_FLASH: 0 GB 64 MB 0.00%

SRAM_DTC_cm7: 183912 B 248 KB 72.42%

SRAM_ITC_cm7: 0 GB 256 KB 0.00%

BOARD_SDRAM: 0 GB 16 MB 0.00%

NCACHE_REGION: 0 GB 16 MB 0.00%

SRAM_OC1: 0 GB 512 KB 0.00%

SRAM_OC2: 0 GB 512 KB 0.00%

SRAM_OC_ECC1: 0 GB 64 KB 0.00%

SRAM_OC_ECC2: 0 GB 64 KB 0.00%

SRAM_OC_cm7: 0 GB 128 KB 0.00%

Then if I redefine it to be:

AT_NONCACHEABLE_SECTION_INIT(uint32_t image_data1[100][100]);

I expect it would move from SRAM_DTC_cm7 to NCACHE_REGION.

But in real life I get the next map:

Memory region Used Size Region Size %age Used

BOARD_FLASH: 0 GB 64 MB 0.00%

SRAM_DTC_cm7: 183912 B 248 KB 72.42%

SRAM_ITC_cm7: 0 GB 256 KB 0.00%

BOARD_SDRAM: 0 GB 16 MB 0.00%

NCACHE_REGION: 40000 B 16 MB 0.24%

SRAM_OC1: 0 GB 512 KB 0.00%

SRAM_OC2: 0 GB 512 KB 0.00%

SRAM_OC_ECC1: 0 GB 64 KB 0.00%

SRAM_OC_ECC2: 0 GB 64 KB 0.00%

SRAM_OC_cm7: 0 GB 128 KB 0.00%

I see it in NCACHE_REGION but using of SRAM_DTC_cm7 area stays the same as before.

Seems it takes memory twice in such a case.

Somebody can please explain why this happens and how to overcome this in such a way it will take memory only in one area (not the default one).

And how to configure the memory if I have to place quite big more then 1M buffer in the RAM( Currently I run my application from internal RAM only).

Kind regards,

Andrei

[AndreiZi]

Hi Diego,

Thank you for your support. You provide me with ample and helpful information.

Kind regards,

Andrei

[AndreiZi]

Hi Diego,

Did you get any explanation about missing 384 Kb internal RAM memory of RT1172?

Kind regards,

Andrei 

[diego_charles]

Hi @AndreiZi 

Yes, thank you for your patience. The advertised 2GB can be calculated as below:

512 KB OCRAM 1 +  64 KB ECC

512 KB OCRAM 2 +  64 KB ECC

512 KB FlexRAM + 128 KB ( see note  1. When ECC is not enabled, the size is OCRAM allocated from FLEXRAM + 128KB OCRAM. When ECC is enabled, the
size is OCRAM allocated from FLEXRAM.  from RM.

256 KB OCRAM from M4  

I highlighted in red the missing memory you are mentioning. Also for the missing 128 KB check AN12077: Using the i.MX RT FlexRAM – Application Note.

I hope this could help you.

Diego

[AndreiZi]

Dear Diego,

Thank you for tis last explanations.

I would like to make it clear for me about your answer:

1. 128KB of memory you mentioned as addition to FlexRAM: is this the same memory as 64 + 64 KB ECC from OCRAM? If it is the same, so you counted it twice :

once here 

512 KB OCRAM 1 +  64 KB ECC

512 KB OCRAM 2 +  64 KB ECC

and second time here:

512 KB FlexRAM + 128 KB 

If it is the same, we still miss 128KB of RAM to put our hand on it

2. The second question is

256 KB OCRAM from M4 is reachable from M7?

And if yes, can you please explain how we can reach from M&? What configurations are need to make?

Kind regards,

Andrei

[diego_charles]

Hi @AndreiZi 

Thank you for your reply, happy to answer. 

Reference manual rev1 tell us that FlexRAM  got its own 128 KB  ECC region and OCRAM1 and OCRAM2 their own 64 KB ECC region. 

Both OCRAM and FlexRAM  provide 2GB of internal SRAM for all RT1170 MCUs. On parts that do not have M4 core, like the RT1171,  OCRAM M4 should still be available as adverstised. Giving us the 2 GB of internal SRAM.

Be aware that the above figure from rev1 is not updated, I used this for my explanation. RM rev 2 merged OCRAM M7 ( FlexRAM) and  OCRAM M7 ( FlexRAM ECC) into a single OCRAM M7, but adding  little note.

Saying that you have FlexRAM of 512 KB + 128 KB might confuse too. So let me explain further.

First, the 128 KB when not used as ECC can be used freely, according to AN12077 : On RT1170, there is a 128-kB ECC-dedicated array ... This array can be freely used as a normal OCRAM data storage until the ECC function is enabled.

Now talking about the 512 KB of FlexRAM. By default, FlexRAM is not setup as 512 KB of OCRAM, like the above screenshots might make you think. FlexRAM is configured as default as : 256 KB DTCM and 256 ITCM.
. 

I hope this could help you. 

Diego

[AndreiZi]

Dear diego_charles,

Thank you for your response. I took your project and tried to make changes in my one to fit your configurations.

For me it did not work exactly as I expected. Here is explanation:

I am trying to utilize the most of internal RAM memory of RT1172, so I defined 2 buffers in 2 different areas of memory:

__attribute__((section(".OCRAM1_Section"))) __attribute__((aligned(4U))) uint32_t image_data1[100][100] = {5,5,5};

__attribute__((section(".OCRAM2_Section"))) __attribute__((aligned(4U))) uint32_t image_data2[100][100] = {7,7,7};

*(.OCRAM1_Section) and *(.OCRAM2_Section) similarly as your MySection. See attached picture (1).

But I realized that my buffers are taking both areas in memory:

Memory region Used Size Region Size %age Used
SRAM_DTC_cm7: 116288 B 248 KB 45.79%
SRAM_ITC_cm7: 0 GB 256 KB 0.00%
BOARD_SDRAM: 0 GB 16 MB 0.00%
NCACHE_REGION: 0 GB 16 MB 0.00%
SRAM_OC1: 40000 B 512 KB 7.63%
SRAM_OC2: 40000 B 512 KB 7.63%
SRAM_OC_ECC1: 0 GB 64 KB 0.00%
SRAM_OC_ECC2: 0 GB 64 KB 0.00%

But when I redefined them as .bss they took the memory only once:

SRAM_DTC_cm7: 36288 B 248 KB 14.29%
SRAM_ITC_cm7: 0 GB 256 KB 0.00%
BOARD_SDRAM: 0 GB 16 MB 0.00%
NCACHE_REGION: 0 GB 16 MB 0.00%
SRAM_OC1: 40000 B 512 KB 7.63%
SRAM_OC2: 40000 B 512 KB 7.63%
SRAM_OC_ECC1: 0 GB 64 KB 0.00%
SRAM_OC_ECC2: 0 GB 64 KB 0.00%
SRAM_OC_cm7: 0 GB 128 KB 0.00%
SRAM_OC_cm7: 0 GB 128 KB 0.00%

I do need to initialize the buffers in my software with non zero values (it should be some RGB pictures), so I think it should be defined as .data section and not as .bss. But I tried to compile it as .bss and it pass the compilation.

Then I did the next (and it worked for me):

Disabled Manage linker script in project properties (picture 2).

Opened the link file and manually changed the lines:

> SRAM_OC1 AT>SRAM_DTC_cm7

> SRAM_OC2 AT>SRAM_DTC_cm7

to

> SRAM_OC1

> SRAM_OC2

Compiled again and got my memory back:

Memory region Used Size Region Size %age Used

SRAM_DTC_cm7: 36288 B 248 KB 14.29%

SRAM_ITC_cm7: 0 GB 256 KB 0.00%

BOARD_SDRAM: 0 GB 16 MB 0.00%

NCACHE_REGION: 0 GB 16 MB 0.00%

SRAM_OC1: 40000 B 512 KB 7.63%

SRAM_OC2: 40000 B 512 KB 7.63%

SRAM_OC_ECC1: 0 GB 64 KB 0.00%

SRAM_OC_ECC2: 0 GB 64 KB 0.00%

SRAM_OC_cm7: 0 GB 128 KB 0.00%

Can you please explain it why we have it in linker

the lines like this:

> SRAM_OC1 AT>SRAM_DTC_cm7

> SRAM_OC2 AT>SRAM_DTC_cm7

Do we actually need it? And what are consequences of such a change?

One more question I have:

In datasheet stated RT1172 has 2MByte of RAM memory.

But I cannot detect all of it. What I found is

512 KB in FlexRAM (divided somehow to DTC,ITC,OCRAM)

512 KB in OCRAM1

512 KB in OCRAM2

128 KB in OCRAM1 ECC / OCRAM2 ECC

So, I still miss 384 KB of RAM.

Can you please point me where it is located and how do I reach it?

Best regards,

Andrei

[diego_charles · Accepted solution]

Hi @AndreiZi 

Thank you for your reply! 

Regarding the below question:

Can you please explain it why we have it in linker

the lines like this:

> SRAM_OC1 AT>SRAM_DTC_cm7

> SRAM_OC2 AT>SRAM_DTC_c

Yes, because of the MCUXpresso linker script. The IDE will try to place most of data and text to the memories that are on the top of the Memory details window. For example if I move SRAM_OC2 to the top:I 

The ld will show   

SRAM_OC1 AT>SRAM_OC2

SRAM_OC2 AT> SRAM_OC2

This is convenient to quickly and effortless link application to certain memory.

Rigth now, If you edit the linker manually, as you did to avoid wasting memory, I can not see issues. General advice would be to verify by running and testing the app.

I am currently checking regarding the missing memory you are mentioning. 

Diego

[diego_charles]

Hi @AndreiZi 

I think that I have replicated your issue, where the array appears to use two sections. Please check below.

AT_NONCACHEABLE_SECTION_INIT (uint32_t image_data1[100][100] __attribute__((aligned(4U))));

 

However, If I use this macro...

__attribute__((section(".MySection"))) uint32_t image_data1[100][100] __attribute__((aligned(4U)))

There is no duplication

Please note that I placed the variable on a extra linker section  (.Mysection) as shown below:

My project is attached for reference. 

The toolchain is MCUXpresso 11.9.1 ( for windows 10 OS), SDK 2.15.1. 

Regarding your second question.

You would need split your buffer on OCRAM1 and OCRAM2, since each one have 512 KB, luckily they are continous.

On the other hand FlexRAM peripheral supports a OCRAM configuration up to  640 KB

I really hope this could help you. 

Diego