MCR[LPRIOEN] fails with mix of standard and extended CAN frames.

[David_Lindqvist]

Local arbitration priority (MCR[LPRIOEN] == 1) fails if both extended and standard frames are activated for transmission simultaneously on MIMXRT1062CVJ5B. In this case the standard frame will always be sent before the extended frame, regardless of both the three PRIO bits and of the ID field. I have only tried it with classical CAN so far (MCR[FD_EN] == 0).

With only std xor ext frames the local arbitration works like the HW manual says and sends the buffer with the lowest PRIO bits. But as soon as there are both std and ext frames activated at the same time, it appears that a std frame always gets sent first. With (MCR[LPRIOEN] == 0) the message to be sent is correctly based on ID bits, RTR, IDE etc. But with (MCR[LPRIOEN] == 1) a 'Standard ID (11 bits)' that is higher than 'Extended ID[28:18] (11 bits)' of an other message buffer, will still be sent out first!

Easiest way to recreate this is to be alone on the bus (i.e. no other units that ACKs). First activate one buffer with EXT ID[28:0] =0 and PRIO bits = 0. Then another buffer with STD ID[11:0] = 0xFF and PRIO[2:0] = 1. Now go bus on with another unit so the messages gets ACKed.

If MCR[LPRIOEN] == 0 the ext frame get sent first, as it should, given the higher priority.

If MCR[LPRIOEN] == 1 the std frame get sent first, even though the PRIO bits says it should be sent after the ext frame.

And just to avoid any speculation: (CTRL1[LBUF] == 0) in all cases above.

You've helped me before @victorjimenez 

Any comments on this or other suggestions on how to send CAN frames in a strictly orderly fashion?

Maybe it should go in another topic but since I can't use the method above (because of my use of a mix of std/ext frames), I can't get two frames to be sent back-to-back in a strictly orderly fashion. Now I use two message buffers for TX and toggle between them. Upon interrupt on one tx message buffer I just write CODE=0xC in the other buffer (all data and ID bits already written in advance). By toggling a gpio pin after setting CODE=0xC I have verified that CODE is written about 3-400 ns into intermission (the name of the time between to consecutive can frames). Using this setup and regardless of the bitrate used, a can frame is then sent after 4 bit times instead of 3 which is the minimum. The problem is that other nodes can start sending after 3 bit times, which means that my second frame will loose arbitration even if has a higher priority.

[Kan_Li]

Hi @David_Lindqvist ,

As arbitration is trigger by the following events, would you please specify which event was used in your test?

The arbitration process is triggered in the following events:
• From the CRC field of the CAN frame. The start point depends on the
CTRL2[TASD] field value. See Control 2 Register (FLEXCAN_CTRL2) for details.
• During the error delimiter field of the CAN frame
• During the Overload Delimiter field of a CAN frame.
• When the winner is inactivated and the CAN bus has still not reached the first bit of
the Intermission field.
• When Arm write to the C/S word of a winner MB and the CAN bus has still not
reached the first bit of the Intermission field.
• When CHI is in Idle state and Arm writes to the C/S word of any MB.
• When FlexCAN exits Bus Off state
• Upon leaving Freeze Mode or Low Power Mode

Please kindly clarify.

Have a great day,
Kan

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