Internal arbitration delays when accessing H/W Registers

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Internal arbitration delays when accessing H/W Registers

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dh1
Contributor II

Hello

When the processor accesses H/W Registers like GPIO data registers or PWM value registers, there seem to be something like wait states where the processor has to wait for the peripheral.

Is there information in the manual what the cause for this delays are or how they can be influenced?

The delays are pretty "expensive" in some places. E.g. the write to two PWM value registers costs over 200ns in our project. This is like 120 processor cycles. We have to do this for 12 PWM submodules, which results in 2.4us only for the update of the PWM values. As we do this every 40us, this is a cpu load of about 6%.

Best regards and Thanks,

Daniel

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dh1
Contributor II

Hi Felipe

Thanks for your reply.

We are using the RT1062.

We used GPIOs to measure the duration. I am aware that this again induces delays. But we did the tests by e.g. writing to 12 PWM registers, and then measure the total duration by setting a gpio output HIGH before, and LOW after the writing of the registers.

And then we could see that the access to the PWM register takes long.

Our code runs in RAM.

Would you expect theses delays? Or how long would you expect one PWM register access to take?

Best regards,

Daniel

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hello Daniel,

 

You could also try to measure CPU load by using SWO profile feature in MCUXpresso, I recommend you to check the following community document created by a colleague. It explains how you can enable Instruction Trace on i.MX RT boards and MCUXpresso.

 

SWO with NXP i.MX RT1064-EVK Board

 

In addition, please provide details in what registers are you reading and facing this behaviors.

 

Best regards,

Felipe

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FelipeGarcia
NXP TechSupport
NXP TechSupport

Hi Daniel,

 

Could you please provide the procedure you are following to measure this? Also please provide the chip you are working on?

 

Best regards,

Felipe

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