IMXRT1602: SPI DMA transmission triggered by external GPIO

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IMXRT1602: SPI DMA transmission triggered by external GPIO

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opcode_x64
Contributor II

Hello,

I want to establish a GPIO triggered SPI-DMA transmission between the IMXRT1602 and an external SPI Device. The external SPI Device provides a "falling" data ready (DRDY) line, which can be used to signalize the SPI Master, here the IMXRT1602, to read out data. To reduce the processor load, I want to use the DMA capability to solve this problem. After some research on the Internet, as here in this forum, I figured out that Crossbar (XBAR) can manage this problem. My strategy/idee would be like this:

Step 1: Taking a XBAR compatible GPIO and configuring this GPIO to work as an XBAR Input which is edge triggered. The configuration of the registers for this is clear for me, since there a lot of examples.

Step 2: Configuring the LPSPI device with all relevant registers: Master, DMA enable etc...

Step 3: Configuring DMA connections (Channel, Source, Destination etc....)

Step 4: This step is not clear for me, since here I have to connect the edge triggered XBAR GPIO to such a XBAR Output which will start the DMA TX and RX transmission. (Actually I need TX to generate SCLK for reading out the data from the external SPI Device)

Does the XBAR Output has to be the XBAR1_OUT00 ("DMA_CH_MUX_REQ30"), which is DMA Channel Request 0 or do I have to use the XBAR1_OUT118 ("LPSPI4_TRG_INPUT").

If I have to use here LPSPI4_TRG_INPUT, then I guess I have to to configure  the LPSPI on external trigger (field HRSEL of Configuration Register 0 of LPSPI).

In other words it is not clear to me if the LPSPI has to be triggered via the XBAR1_OUT118  to start the TX of the LPSPI or will the LPSPI start the transmission over the DMA automaticaly when the XBAR1_OUT00 ("DMA_CH_MUX_REQ30") is triggered.

 

Thank you !

Best regards,

opcode_x64

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8 Replies

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FelipeGarcia
NXP Employee
NXP Employee

Hi,

In my opinion you will need to use XBAR1_OUT00 as if you need DMA to be triggered by XBAR GPIO you will need to configure DMA Mux for this not LPSPI mux option.

FelipeGarcia_0-1616692105341.png

Best regards,

Felipe

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2,099 Views
opcode_x64
Contributor II

Hello Felipe,

when I have understand you correctly,  I have to trigger the LPSPI4 at DMAMUX_SOURCE_XBAR1_0. In the XBAR setting I have connected XBARA1_IN_IOMUX_XBAR_INOUT08 to  XBARA1_OUT_DMA_CH_MUX_REQ30. So when the XBAR input triggers, it will start a dma request on channel 0 and sametime it will trigger the LPSPI4 to start the transfer (generating SCLK).

Is this correct ?

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mjbcswitzerland
Specialist V

Hi

You may already have all info for the XBAR and DMA triggering but if not there is a video about its operation here:
https://youtu.be/zNWIG-O7ZW0

In your particular case I would be tempted to prepare all of the data to be transmitted in a buffer and set up a DMA channel to transfer it based on SPI output empty DMA trigger but not start the transfer yet.

Then use the GPIO input DMA trigger to cause a write to the DMA enable register (single long word transfer of the correct value) and thus kicking it off.

There are various variations but this one is very simple to achieve.

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training, solutions to problems or rapid product development requirements

For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: https://www.utasker.com/iMX/RT1060.html

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2,067 Views
opcode_x64
Contributor II

Hello Mark (mjbcswitzerland),

thanks for your reply and your solution approach. Sorry for the late reply.. a lot of other work to do...

I want to summarize shortly how I got it to work, whereby it is similiar to your approach:

Step 1: Configuration of XBAR based GPIO input trigger:

I used  GPIO_EMC_06, which is the XBAR IO named  XBAR INOUT 08 and configurated it as XBAR input (Using Register: IOMUXC_GPR_GPR6) triggering at falling edge (Using Register: XBARA1_CTRL0)
Then I connected this XBAR INOUT08 to XBARA1_OUT_DMA_CH_MUX_REQ30

Functional summary of Step 1: A falling edge at GPIO_EMC_06 will trigger a DMA request on DMA Channel 0 (yes not 30!! Please look carefully in the Reference Manual of IMXRT1602. The 30 does not stand for the Channel number)

##########################
Step 2: Configuration of DMA Channel 0 to activate the DMA Channel 1 of LPSPI4 TX:

To trigger the LPSPI4 TX DMA request on occurance of a falling edge at the XBAR INOUT08 I use a DMA channel which writes to DMA_SERQ register the corresponding
bit of the DMA Channel used for the LPSPI4 TX, for example DMA Channel 1, since the DMA Channel for writing the DMA_SERQ Register is DMA Channel 0. The DMA channel 0
for writing the corresponding bit to the DMA_SERQ register is set to be triggered on XBAR1 trigger DMAMUX_SOURCE_XBAR1_0.
The LPSPI4 is configurated as: MASTER, NO RX STALL and TDDE as well as RDDE enabled (automatic DMA Requests vor TX and RX, when the TX and RX FiFo's are empty)

Functional summary of Step 2: As described in Step 1, the falling edge at the GPIO_EMC_06 will trigger a DMA request of DMA Channel 0. The DMA Channel 0 writes the corresponding
bit for DMA Channel 1 in the DMA_SERQ register to activate (enable) the DMA Channel 1 which is used for DMA LPSPI4 TX. The DMA Channel 1 is set to be triggered on DMAMUX_SOURCE_LPSPI4_TX

##########################
Step 3: Configuration of the DMA Channel for LPSPI RX:

When also LPSPI4 RX is needed, one can use a further DMA Channel, for example, channel 2 for reading SPI data in, when data is output (TX). The DMA Channel 2 is set
to be triggered on DMAMUX_SOURCE_LPSPI4_RX.

Some more informations:
----------------------------------------------------------
DMA Channel 0:
Source=Memory(Variable) where the corresponding bit value is stored for the DMA_SERQ register to activate DMA Channel 1 which is the value 1
Destination=Address of DMA_SERQ Register
Trigger at hardware event: DMAMUX_SOURCE_XBAR1_0
----------------------------------------------------------
DMA Channel 1:
Source=Memory Address of the TX data array, e.g. byte array.
Destination=LPSPI4_TDR (Transmit Data Register)
Trigger at hardware event: DMAMUX_SOURCE_LPSPI4_TX
----------------------------------------------------------
DMA Channel 2:
Source=LPSPI4_RDR Receive Data Register)
Destination=Memory Address of the RX data array, e.g. byte array.
Trigger at hardware event: DMAMUX_SOURCE_LPSPI4_RX
----------------------------------------------------------

Since I am using the Arduino Environment of the Teensy 4.1 board some of the names such as registers can differ from the "original" names in the reference manual. Also
I did not post the Arduino Code, since it will not be so useful for the NXP development environment, because of the "special" libraries used for DMA channel configuration
within the Arduino Environment.

However, I hope this can help also NXP coders.

Best regards,
opcode_x64

2,115 Views
opcode_x64
Contributor II

Hello Felipe, 

thank you for your reply. But how will the LPSPI know to start the Rx / Tx? Or does the LPSPI starts automaticaly when it is configured for DMA and a service request is initiated by the XBAR1_OUT00 through the GPIO?   

Best regards, 

opcode_x64     

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2,113 Views
opcode_x64
Contributor II

I think I got it. I have to connect XBAR1_OUT1 with DMA Mux 79 for LPSPI RX or DMA Mux 79 for LPSPI for TX. 

 

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2,116 Views
opcode_x64
Contributor II

Hello Felipe, 

thank you for your reply. But how will the LPSPI know to start the Rx / Tx? Ort does the LPSPI starts automaticaly when it is configured for DMA and a service request is initiated by the XBAR1_OUT00 through the GPIO?   

Best regards, 

opcode_x64     

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2,132 Views
opcode_x64
Contributor II

Bump + No ideas ?

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