We have a design working using a 1064. We have created our own board design around the 1064 EVK, using the reference ORCAD files as a starting point, we have used 4 layers and directly copied the design of the EVK with the same trace lengths, board stack up etc.
When we use near field probes most of the noise has a 48Mhz harmonic, and is worst on the SDRAM address and data bus.
The design is failing CE compliance, we have added series termination for the SDRAM clock.
Has anyone successfully completed a design based around the EVK layout?
The app-note below shows the results of enabling spread spectrum on the RT1170.
Admittedly that app-note is a little thin in the implementation department. But you just need to edit two registers:
Section 184.108.40.206.2 System PLL (PLL2) in the RT1064 Reference Manual gives the equations to adjust the frequency spread and modulation rate.
If you look at the sample code shown in the app-note you'll find that for the 6MHz spread spectrum enablement they used the following settings:
CCM_ANALOG_PLL_SYS_SS[STOP] = 0x240
CCM_ANALOG_PLL_SYS_SS]STEP] = 0x6
CCM_ANALOG_PLL_SYS_DENOM[B] = 0x960
With the reference Frequency = 24MHz this gives a frequency spread = 5.76MHz and a modulation frequency = 125kHz.
R0_6 is the second lowest impedance option - 26Ohm at 3.3V. The test code we used set it to R0_4 which is 39Ohms at 3.3V. Try using R0_4.
Thanks for your response John Phillipe we have now greatly reduced the emissions from the memory. WE set the drive to R0, and fitted a 22 ohm series resistor ( on the reference design it is 0R) on the SDRAM clock.
One further question in respect of the display, we are seeing a 33MHz fundamental from the display. We have set the drive to R0, and the clock has been rounded and the display works fine, is there any way of implementing spread spectrum on the display lines?
Only the PLL2 of the RT1064 has the spread spectrum feature. But you can change the clock source for the LCDIF. Assuming 33MHz is your desired LCD clock rate then you could select PLL2 as the source, and then set the LCDIF_PRED value to 8 and the LCDIF_PODF value to 2 which gives 528MHz / 8 / 2 = 33MHz.
I believe the default clock source for LCDIF is the PLL5 but the reset value in the reference manual says it's PLL3 PFD1.
Bad luck - I feel your pain ;-(
4-layers boards can be a nightmare to pass EMI, for all sorts of reasons but a couple of main ones being - it's very difficult to change layers without causing field spread, and most often the centre core is ~ 1.0mm thick (if the overall thickness is 1.6mm) which means you have increased inductance between L1/2 and L3/4.
I would probably analyse the design and identify the high speed nets (rise/fall time, not clock frequency) and wherever possible these nets should be routed over a tightly coupled ground plane, with no layer transitions. Power bus impedance is also important, also look carefully at the layer stackup.
I have seen improvements in EMI signature of 20 dB or more by paying careful attention to these points.
My personal opinion is that for all but the simplest designs, 4-layers is really pushing it when you have a MCU with this number of pins in the BGA pin field that you need to get escaped. 6-layers is way, way better and often only ~ 15% cost add. If you go to 6-layers, try and make L2 and L5 both solid ground and use L1-L3 and L4-L6 as routing pairs.
I’m sorry to hear that you are having EMC problems on your board. The recommended hardware design guidelines for the i.MXRT1064 can be found on the following document:
Section 7.4 covers the SDRAM design which is critical due to the signal frequencies.
There are some other variables to keep in mind, such as the dielectric laminate on the PCB. There are some general guidelines on the following Application Note.
Hopefully some community users may be able to provide additional insights-
Thanks for responding to my Query and the links. As we have directly copied the routing from the evaluation board, I would have assumed that we followed the guidelines. I have fitted the series termination to the SDRAM clock, and looking at similar designs I don't see any reference to other termination resistors. I compared the emissions against a LPC178X design with the same SDRAM, and this emits 10-15db less for a bus clock rate of 80MHz.
I ran the application code directly on the 1064 Evaluation board and the emissions were exactly the same as our board, when we discussed this our external firmware consultant he noted that the evaluation board caused his DAB radio to stop working.
So I suppose I have 2 questions, firstly was any testing done with evaluation board with the SDRAM as frame buffer and a display attached, and secondly has anyone used the 4 layer approach and passed EMC when using the SDRAM as a frame buffer?
The RT1064 did go through FCC testing exercising the SDRAM. A couple of questions:
1. Have you probed the SDRAM clock/address lines in question?
2. Have you tried adjusting the drive strength of the SDRAM GPIO pins?
3. Have you enabled the spread spectrum feature on the SDRAM clock?
Thanks John Phillippe, would it be possible to share the project used and the associated configuration file. I suspect we have used the defaults when creating the .mex file.
You can share your project/config files. It might be faster for you to simply adjust the drive strength of the sdram pins and use an oscilloscope to find the "critically damped" setting. If you don't have a scope available then you can try and reduce the drive strength a step at a time and then re-run your code. If it passes then reduce the drive strength again and re-run. Repeat this procedure until your code fails. Then just use the drive strength setting of the previous passing run.
What other changes from the EVK did you make? Are there any pins you didn't route out but then didn't disable in your code?