How to use on board external SDRAM for global variables?

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How to use on board external SDRAM for global variables?

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ping1
Contributor IV

Hello, All

I need to put some variables on external SDRAM, have run the example evkmimxrt1024_semc, understand it needs configuration, and variables are there in local pointer, but if I need to put some variables there like __DATA(RAM4) uint32_t sdram_data[512],  RAM4 is default on board RAM starts at 0x80000000. when it runs, it comes with a hard fault.

What else do I need to do in order to use the external RAM please? I am using RT1024_EVK and MCUXpresso v11.3.

Regards!

Ping

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mjbcswitzerland
Specialist V

Hi

If you import any SDK project using SDRAM for its execution it will give you a DCD setup.

Below is the DCD that can be used with all EVKs with SDRAM in the uTasker project which is built up in a more readable form that the ones in the SDK and so will allow you to better understand the actual content - but both give the same result.

Regards

Mark

 

        #define GROUP1_ENTRIES       117
        #define GROUP2_ENTRIES       2
        #define GROUP3_ENTRIES       2
        #define GROUP4_ENTRIES       3
        #define GROUP5_ENTRIES       1

        typedef struct _PACK stDCD_TABLE {
            DCD_HEADER    dcd_header;
            unsigned char dcd_command1[GROUP_SIZE(GROUP1_ENTRIES)];
            unsigned char dcd_wait1[DCD_WAIT_SIZE];
            unsigned char dcd_command2[GROUP_SIZE(GROUP2_ENTRIES)];
            unsigned char dcd_wait2[DCD_WAIT_SIZE];
            unsigned char dcd_command3[GROUP_SIZE(GROUP3_ENTRIES)];
            unsigned char dcd_wait3[DCD_WAIT_SIZE];
            unsigned char dcd_command4[GROUP_SIZE(GROUP4_ENTRIES)];
            unsigned char dcd_wait4[DCD_WAIT_SIZE];
            unsigned char dcd_command5[GROUP_SIZE(GROUP5_ENTRIES)];
        } DCD_TABLE;

        #if defined _COMPILE_IAR
        __root const DCD_TABLE __dcd_data @ ".boot_hdr.dcd_data" // __root forces the function to be linked in IAR project
        #elif defined _GNU
        static const DCD_TABLE __attribute__((section(".boot_hdr.dcd_data"))) __dcd_data
        #elif defined _COMPILE_KEIL
        __attribute__((section("_DCD_DATA"))) const DCD_TABLE __dcd_data
        #else
        static const DCD_TABLE __dcd_data                                        // IS42S16160J-6BLI SDRAM configuration
        #endif
        = {
            { DCD_TAG, {BIG_SHORT_WORD_BYTES(sizeof(DCD_TABLE))}, DCD_VERSION }, // header
            {   // Command group 1
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP1_ENTRIES),
                _DCD_WRITE_LONG_WORD(CCM_CCGR0, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR1, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR2, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR3, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR4, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR5, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR6, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_ANALOG_PLL_SYS, (CCM_ANALOG_PLL_SYS_ENABLE | CCM_ANALOG_PLL_SYS_DIV_SELECT)), // enable the system PLL (PLL2)
                _DCD_WRITE_LONG_WORD(CCM_ANALOG_PFD_528, (29 << 16)), // system PLL PFD2 fractional mask for 327.7241379MHz
              //_DCD_WRITE_LONG_WORD(CCM_ANALOG_PFD_528, (35 << 16)), // system PLL PFD2 fractional mask for 271.5428571MHz
                _DCD_WRITE_LONG_WORD(CCM_CBCDR, (CCM_CBCDR_SEMC_PODF_DIV2 | CCM_CBCDR_AHB_PODF_DIV4 | CCM_CBCDR_IPG_PODF_DIV2 | CCM_CBCDR_SEMC_CLK_SEL_SEMC | CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2_PFD2)), // select SEMC_CLK_ROOT from PLL2-PFD2 divided by 2 to give 163.86MHz (max. 166MHz)
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, GPIO_EMC_00_SEMC_DATA00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, GPIO_EMC_01_SEMC_DATA01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, GPIO_EMC_02_SEMC_DATA02),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, GPIO_EMC_03_SEMC_DATA03),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, GPIO_EMC_04_SEMC_DATA04),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, GPIO_EMC_05_SEMC_DATA05),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, GPIO_EMC_06_SEMC_DATA06),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, GPIO_EMC_07_SEMC_DATA07),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, GPIO_EMC_08_SEMC_DM00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, GPIO_EMC_09_SEMC_ADDR00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, GPIO_EMC_10_SEMC_ADDR01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, GPIO_EMC_11_SEMC_ADDR02),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, GPIO_EMC_12_SEMC_ADDR03),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, GPIO_EMC_13_SEMC_ADDR04),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, GPIO_EMC_14_SEMC_ADDR05),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, GPIO_EMC_15_SEMC_ADDR06),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, GPIO_EMC_16_SEMC_ADDR07),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, GPIO_EMC_17_SEMC_ADDR08),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, GPIO_EMC_18_SEMC_ADDR09),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, GPIO_EMC_19_SEMC_ADDR11),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, GPIO_EMC_20_SEMC_ADDR12),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, GPIO_EMC_21_SEMC_BA0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, GPIO_EMC_22_SEMC_BA1),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, GPIO_EMC_23_SEMC_ADDR10),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, GPIO_EMC_24_SEMC_CAS),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, GPIO_EMC_25_SEMC_RAS),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, GPIO_EMC_26_SEMC_CLK),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, GPIO_EMC_27_SEMC_CKE),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, GPIO_EMC_28_SEMC_WE),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, GPIO_EMC_29_SEMC_CS0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, GPIO_EMC_30_SEMC_DATA08),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, GPIO_EMC_31_SEMC_DATA09),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, GPIO_EMC_32_SEMC_DATA10),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, GPIO_EMC_33_SEMC_DATA11),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, GPIO_EMC_34_SEMC_DATA12),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, GPIO_EMC_35_SEMC_DATA13),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, GPIO_EMC_36_SEMC_DATA14),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, GPIO_EMC_37_SEMC_DATA15),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, GPIO_EMC_38_SEMC_DM01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, IOMUXC_SW_MUX_CTL_PAD_SION),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, GPIO_EMC_40_SEMC_RDY),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, GPIO_EMC_41_SEMC_CSX0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
    #if defined iMX_RT1062
        #if defined APPLICATION_REQUIRES_GPIO_EMC_39
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_BTO_DEFAULT)),  // dummy read strobe loopbacked internally reduces the maximum speed of operation
        #else
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_BTO_DEFAULT | SEMC_MCR_DQSMD)),
        #endif
    #else
        #if defined APPLICATION_REQUIRES_GPIO_EMC_39
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (0)),                     // dummy read strobe loopbacked internally reduces the maximum speed of operation
        #else
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_DQSMD)),        // DQS(read strobe) mode
        #endif
    #endif
                _DCD_WRITE_LONG_WORD(SEMC_BMCR0, 0x00030524),            // queue A weigth settings
                _DCD_WRITE_LONG_WORD(SEMC_BMCR1, 0x06030524),            // queue B weigth settings
                _DCD_WRITE_LONG_WORD(SEMC_BR0,  (SDRAM_ADDR | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 0
                _DCD_WRITE_LONG_WORD(SEMC_BR1,  ((SDRAM_ADDR + (32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 1
                _DCD_WRITE_LONG_WORD(SEMC_BR2,  ((SDRAM_ADDR + (2 * 32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 2
                _DCD_WRITE_LONG_WORD(SEMC_BR3,  ((SDRAM_ADDR + (3 * 32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 3
                _DCD_WRITE_LONG_WORD(SEMC_BR4,  ((SDRAM_ADDR + (256 * 1024 * 1024)) | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 4
                _DCD_WRITE_LONG_WORD(SEMC_BR5,  ((SDRAM_ADDR + (2 * 256 * 1024 * 1024)) | SEMC_BR_MS_16MB | SEMC_BR_VLD)), // base 5
                _DCD_WRITE_LONG_WORD(SEMC_BR6,  ((SDRAM_ADDR + (((2 * 256) + 132) * 1024 * 1024)) | SEMC_BR_MS_8MB | SEMC_BR_VLD)), // base 6
                _DCD_WRITE_LONG_WORD(SEMC_BR7,  ((SDRAM_ADDR + (((2 * 256) + 132 + 16) * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 7
                _DCD_WRITE_LONG_WORD(SEMC_BR8,  (0 | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 8
                _DCD_WRITE_LONG_WORD(SEMC_IOCR, (SEMC_IOCR_MUX_RDY_NAND_RDY_WAIT |SEMC_IOCR_MUX_CSX3_DBI_CSX | SEMC_IOCR_MUX_CSX2_NAND_CE | SEMC_IOCR_MUX_CSX1_PSRAM_CE | SEMC_IOCR_MUX_CSX0_NOR_CE | SEMC_IOCR_MUX_A8_SDRAM_A8)),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR0, 0x00000f31),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR1, 0x00652922),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR2, 0x00010920),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR3, 0x50210a08),
                _DCD_WRITE_LONG_WORD(SEMC_DBICR0, 0x00000021),
                _DCD_WRITE_LONG_WORD(SEMC_DBICR1, 0x00888888),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR1, 0x00000002),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR2, 0x00000000),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, 0x80000000),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_PRECHARGE_ALL)),
            },
            {   // Wait 1
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 2
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP2_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH)),
            },
            {   // Wait 2
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 3
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP3_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH)),
            },
            {   // Wait 3
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 4
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP4_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPTXDAT, (0x00000033)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_MODESET)),
            },
            {   // Wait 4
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 5
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP5_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR3, (0x50210a08 | SEMC_SDRAMCR3_REN)),
            },
        };

 

 

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ping1
Contributor IV

Thanks, Mark

any examples or procedures about how to configure DCD please?

Regards!

Ping

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mjbcswitzerland
Specialist V

Hi

If you import any SDK project using SDRAM for its execution it will give you a DCD setup.

Below is the DCD that can be used with all EVKs with SDRAM in the uTasker project which is built up in a more readable form that the ones in the SDK and so will allow you to better understand the actual content - but both give the same result.

Regards

Mark

 

        #define GROUP1_ENTRIES       117
        #define GROUP2_ENTRIES       2
        #define GROUP3_ENTRIES       2
        #define GROUP4_ENTRIES       3
        #define GROUP5_ENTRIES       1

        typedef struct _PACK stDCD_TABLE {
            DCD_HEADER    dcd_header;
            unsigned char dcd_command1[GROUP_SIZE(GROUP1_ENTRIES)];
            unsigned char dcd_wait1[DCD_WAIT_SIZE];
            unsigned char dcd_command2[GROUP_SIZE(GROUP2_ENTRIES)];
            unsigned char dcd_wait2[DCD_WAIT_SIZE];
            unsigned char dcd_command3[GROUP_SIZE(GROUP3_ENTRIES)];
            unsigned char dcd_wait3[DCD_WAIT_SIZE];
            unsigned char dcd_command4[GROUP_SIZE(GROUP4_ENTRIES)];
            unsigned char dcd_wait4[DCD_WAIT_SIZE];
            unsigned char dcd_command5[GROUP_SIZE(GROUP5_ENTRIES)];
        } DCD_TABLE;

        #if defined _COMPILE_IAR
        __root const DCD_TABLE __dcd_data @ ".boot_hdr.dcd_data" // __root forces the function to be linked in IAR project
        #elif defined _GNU
        static const DCD_TABLE __attribute__((section(".boot_hdr.dcd_data"))) __dcd_data
        #elif defined _COMPILE_KEIL
        __attribute__((section("_DCD_DATA"))) const DCD_TABLE __dcd_data
        #else
        static const DCD_TABLE __dcd_data                                        // IS42S16160J-6BLI SDRAM configuration
        #endif
        = {
            { DCD_TAG, {BIG_SHORT_WORD_BYTES(sizeof(DCD_TABLE))}, DCD_VERSION }, // header
            {   // Command group 1
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP1_ENTRIES),
                _DCD_WRITE_LONG_WORD(CCM_CCGR0, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR1, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR2, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR3, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR4, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR5, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_CCGR6, (0xffffffff)),
                _DCD_WRITE_LONG_WORD(CCM_ANALOG_PLL_SYS, (CCM_ANALOG_PLL_SYS_ENABLE | CCM_ANALOG_PLL_SYS_DIV_SELECT)), // enable the system PLL (PLL2)
                _DCD_WRITE_LONG_WORD(CCM_ANALOG_PFD_528, (29 << 16)), // system PLL PFD2 fractional mask for 327.7241379MHz
              //_DCD_WRITE_LONG_WORD(CCM_ANALOG_PFD_528, (35 << 16)), // system PLL PFD2 fractional mask for 271.5428571MHz
                _DCD_WRITE_LONG_WORD(CCM_CBCDR, (CCM_CBCDR_SEMC_PODF_DIV2 | CCM_CBCDR_AHB_PODF_DIV4 | CCM_CBCDR_IPG_PODF_DIV2 | CCM_CBCDR_SEMC_CLK_SEL_SEMC | CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2_PFD2)), // select SEMC_CLK_ROOT from PLL2-PFD2 divided by 2 to give 163.86MHz (max. 166MHz)
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, GPIO_EMC_00_SEMC_DATA00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, GPIO_EMC_01_SEMC_DATA01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, GPIO_EMC_02_SEMC_DATA02),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, GPIO_EMC_03_SEMC_DATA03),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, GPIO_EMC_04_SEMC_DATA04),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, GPIO_EMC_05_SEMC_DATA05),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, GPIO_EMC_06_SEMC_DATA06),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, GPIO_EMC_07_SEMC_DATA07),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, GPIO_EMC_08_SEMC_DM00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, GPIO_EMC_09_SEMC_ADDR00),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, GPIO_EMC_10_SEMC_ADDR01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, GPIO_EMC_11_SEMC_ADDR02),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, GPIO_EMC_12_SEMC_ADDR03),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, GPIO_EMC_13_SEMC_ADDR04),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, GPIO_EMC_14_SEMC_ADDR05),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, GPIO_EMC_15_SEMC_ADDR06),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, GPIO_EMC_16_SEMC_ADDR07),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, GPIO_EMC_17_SEMC_ADDR08),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, GPIO_EMC_18_SEMC_ADDR09),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, GPIO_EMC_19_SEMC_ADDR11),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, GPIO_EMC_20_SEMC_ADDR12),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, GPIO_EMC_21_SEMC_BA0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, GPIO_EMC_22_SEMC_BA1),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, GPIO_EMC_23_SEMC_ADDR10),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, GPIO_EMC_24_SEMC_CAS),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, GPIO_EMC_25_SEMC_RAS),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, GPIO_EMC_26_SEMC_CLK),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, GPIO_EMC_27_SEMC_CKE),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, GPIO_EMC_28_SEMC_WE),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, GPIO_EMC_29_SEMC_CS0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, GPIO_EMC_30_SEMC_DATA08),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, GPIO_EMC_31_SEMC_DATA09),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, GPIO_EMC_32_SEMC_DATA10),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, GPIO_EMC_33_SEMC_DATA11),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, GPIO_EMC_34_SEMC_DATA12),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, GPIO_EMC_35_SEMC_DATA13),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, GPIO_EMC_36_SEMC_DATA14),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, GPIO_EMC_37_SEMC_DATA15),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, GPIO_EMC_38_SEMC_DM01),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, IOMUXC_SW_MUX_CTL_PAD_SION),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, GPIO_EMC_40_SEMC_RDY),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, GPIO_EMC_41_SEMC_CSX0),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
                _DCD_WRITE_LONG_WORD(IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, (IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)),
    #if defined iMX_RT1062
        #if defined APPLICATION_REQUIRES_GPIO_EMC_39
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_BTO_DEFAULT)),  // dummy read strobe loopbacked internally reduces the maximum speed of operation
        #else
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_BTO_DEFAULT | SEMC_MCR_DQSMD)),
        #endif
    #else
        #if defined APPLICATION_REQUIRES_GPIO_EMC_39
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (0)),                     // dummy read strobe loopbacked internally reduces the maximum speed of operation
        #else
                _DCD_WRITE_LONG_WORD(SEMC_MCR, (SEMC_MCR_DQSMD)),        // DQS(read strobe) mode
        #endif
    #endif
                _DCD_WRITE_LONG_WORD(SEMC_BMCR0, 0x00030524),            // queue A weigth settings
                _DCD_WRITE_LONG_WORD(SEMC_BMCR1, 0x06030524),            // queue B weigth settings
                _DCD_WRITE_LONG_WORD(SEMC_BR0,  (SDRAM_ADDR | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 0
                _DCD_WRITE_LONG_WORD(SEMC_BR1,  ((SDRAM_ADDR + (32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 1
                _DCD_WRITE_LONG_WORD(SEMC_BR2,  ((SDRAM_ADDR + (2 * 32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 2
                _DCD_WRITE_LONG_WORD(SEMC_BR3,  ((SDRAM_ADDR + (3 * 32 * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 3
                _DCD_WRITE_LONG_WORD(SEMC_BR4,  ((SDRAM_ADDR + (256 * 1024 * 1024)) | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 4
                _DCD_WRITE_LONG_WORD(SEMC_BR5,  ((SDRAM_ADDR + (2 * 256 * 1024 * 1024)) | SEMC_BR_MS_16MB | SEMC_BR_VLD)), // base 5
                _DCD_WRITE_LONG_WORD(SEMC_BR6,  ((SDRAM_ADDR + (((2 * 256) + 132) * 1024 * 1024)) | SEMC_BR_MS_8MB | SEMC_BR_VLD)), // base 6
                _DCD_WRITE_LONG_WORD(SEMC_BR7,  ((SDRAM_ADDR + (((2 * 256) + 132 + 16) * 1024 * 1024)) | SEMC_BR_MS_32MB | SEMC_BR_VLD)), // base 7
                _DCD_WRITE_LONG_WORD(SEMC_BR8,  (0 | SEMC_BR_MS_256MB | SEMC_BR_VLD)), // base 8
                _DCD_WRITE_LONG_WORD(SEMC_IOCR, (SEMC_IOCR_MUX_RDY_NAND_RDY_WAIT |SEMC_IOCR_MUX_CSX3_DBI_CSX | SEMC_IOCR_MUX_CSX2_NAND_CE | SEMC_IOCR_MUX_CSX1_PSRAM_CE | SEMC_IOCR_MUX_CSX0_NOR_CE | SEMC_IOCR_MUX_A8_SDRAM_A8)),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR0, 0x00000f31),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR1, 0x00652922),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR2, 0x00010920),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR3, 0x50210a08),
                _DCD_WRITE_LONG_WORD(SEMC_DBICR0, 0x00000021),
                _DCD_WRITE_LONG_WORD(SEMC_DBICR1, 0x00888888),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR1, 0x00000002),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR2, 0x00000000),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, 0x80000000),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_PRECHARGE_ALL)),
            },
            {   // Wait 1
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 2
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP2_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH)),
            },
            {   // Wait 2
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 3
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP3_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH)),
            },
            {   // Wait 3
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 4
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP4_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_IPTXDAT, (0x00000033)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCR0, (0x80000000)),
                _DCD_WRITE_LONG_WORD(SEMC_IPCMD, (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_MODESET)),
            },
            {   // Wait 4
                //
                _BCD_WAIT_SET(SEMC_INTR, SEMC_INTR_IPCMDDONE),
            },
            {   // Command group 5
                //
                _DCD_WRITE_LONG_WORD_GROUP(GROUP5_ENTRIES),
                _DCD_WRITE_LONG_WORD(SEMC_SDRAMCR3, (0x50210a08 | SEMC_SDRAMCR3_REN)),
            },
        };

 

 

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ping1
Contributor IV

Found the example - Hello World uses it.

Thanks!

Ping

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mjbcswitzerland
Specialist V

Hi

For the linker SDRAM and SRAM are the same so you can put global variables anywhere.

However make sure that the SDRAM is initialised before the initialisation routine copies initialised data to an area in SDRAM (or clears .bss section in SDRAM) otherwise it will fault during this operation.

Usually SDRAM is configured by DCD in the boot section and so is immediately ready for use, - if you use an example it may be that the example is showing configuration of SDRAM  in code and so it will fail if variables were to be located there - in such a case avoid an SDRAM demonstration since it will not be suitable for such operation.

Regards

Mark [uTasker project developer for Kinetis and i.MX RT]


For professionals searching for faster, problem-free Kinetis and i.MX RT 10xx developments the uTasker project holds the key: https://www.utasker.com/iMX/RT1024.html

 

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