Does a RT1064 FlexSPI DMA driver exist?

[chunk]

The MCUXpresso SDK API Reference documents a FlexSPI eDMA driver in version 2.7 and prior. The Change Log also mentions an update to the FLEXSPI_TransferEDMA function, which is supposedly part of the FlexSPI eDMA driver.

However, it cannot be found in any available version of the SDK itself. There is no mention of its removal in either the Change Log or the Deprecated List, though version 2.8 of the SDK API reference drops any mention of the FlexSPI eDMA driver.

Does this driver actually exist or has it ever existed? If so, where can I find it?

[kerryzhou · Accepted solution]

Hi chunk,

   Thanks for your interest in the NXP MIMXRT product, I would like to provide service for you.

   I checked the newest RT1064 SDK flexSPI drivers, still no DMA related drivers.

   But, fortunately, we have an application note about the RT flexSPI, it has the flexSPI DMA code, please check the application note:

  https://www.nxp.com/docs/en/application-note/AN12564.pdf

https://www.nxp.com/docs/en/application-note-software/AN12564SW.zip

status_t FLEXSPI_TransferBlocking_DMA(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
{
    uint32_t configValue = 0;
    status_t result = kStatus_Success;

    /* Clear sequence pointer before sending data to external devices. */
    base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;

    /* Clear former pending status before start this tranfer. */
    base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
                  FLEXSPI_INTR_IPCMDGE_MASK;

    /* Configure base addresss. */
    base->IPCR0 = xfer->deviceAddress;

    /* Reset fifos. */
    base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
    base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;

    /* Configure data size. */
    if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
    {
        configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize);
    }

    /* Configure sequence ID. */
    configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1);
    base->IPCR1 = configValue;

    //disable interrupt setting.
    uint32_t regPrimask = DisableGlobalIRQ();
    
    /* Start Transfer. */
    if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config))
    {
        result = FLEXSPI_WriteBlocking_DMA(base, xfer->data, xfer->dataSize);
    }
    else if (xfer->cmdType == kFLEXSPI_Read)
    {
        base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
        result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
    }
    else
    {
        base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;
    }
    /* Wait for bus idle. */
    while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
    {
    }
    
    //restore interrupt setting.
    EnableGlobalIRQ(regPrimask);
    
    

    if (xfer->cmdType == kFLEXSPI_Command)
    {
        result = FLEXSPI_CheckAndClearError(base, base->INTR);
    }

    return result;
}

Wish it helps you!

If you still have questions about it, please kindly let me know.

Kerry

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[chunk]

Thanks! That will help jump start my development. Any idea why there is documentation for a non-existent API?

[kerryzhou]

Hi chunk,

  My understanding is the document has the bugs or just write it, and the related DMA API will added to the SDK in the future, you can understand that the document is released in advance.

   Anyway, you can refer to the AN and the related code at first.

Wish it helps you!

If you still have questions about it, please kindly let me know!

Best Regards,

Kerry

-------------------------------------------------------------------------------

Note:

- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored

Please open a new thread and refer to the closed one, if you have a related question at a later point in time.

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