Custom Hardware IMXRT1052 External Flash booting

_bjs · ‎07-05-2022

Hello our company has purchased 1500 units of NXP IMXRT1052DVL6B IC.
I am responsible for getting our STM32F7 GUI program running on the IMXRT1052.
The porting of the software, EMwin, I2C, SPI, LCD, FreeRTOS etc. libraries i am capable on my own.
However the XIP, IVT, eFuses, DCD, are new to me.

I am a higher level programmer and not comfortable with this.

I have used the IMXRT1050-EVKB and SEGGER to get the external flash to work, when i have iled-Blinky project programmed with different blink rates, it remembers after power-on/off.

Now i am moving to the custom hardware which is using the same IS25LP064 (we use JMLE, EVKB uses AJBLE). I have working demo 'freertos_hello_flash_operation'. I use the same project from the IMXRT1050-EVKB and program it onto our custom hardware, with use of MCUXpresso IDE, the Segger program is not entering Main, but is going to ResetISR().

I am now unsure what i need to do (voltage of QSPI chip on startup?, DCD registers? IVT? hidden eFuses? boot config same as on the EVKB board).

Please help me.

I provide the settings i use to get the Iled-Blinky IMXRT1050-EVKB to remember:
XIP NOR Config.c -

const flexspi_nor_config_t qspiflash_config = {
  .memConfig = {
    .tag = FLEXSPI_CFG_BLK_TAG,
    .version = FLEXSPI_CFG_BLK_VERSION,
    .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,
    .csHoldTime = 3,
    .csSetupTime = 3,
    .columnAddressWidth = 0,
	.sflashPadType = kSerialFlash_4Pads,
	.serialClkFreq = kFlexSpiSerialClk_100MHz,
	.lutCustomSeqEnable = 0u,
    .sflashA1Size = 8u * 1024u * 1024u,
    .lookupTable = {
      //
      // Configure LUT for read
      //
      FLEXSPI_LUT_SEQ(CMD_SDR,   FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
      FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR,  FLEXSPI_4PAD, 0x02),
    },
  },
  .pageSize = 256u,
  .sectorSize = 4u* 1024u,
  .blockSize = 256u * 124u,
  .isUniformBlockSize = false,
};

MCU settings :

Symbols:

DCD:
group: 'Imported Commands'
#1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4
#1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4
#1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4
#1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4
#1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4
#1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4
#1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4
#1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4
#1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4
#1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4
#1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4
#1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4
#1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4
#1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4
#1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4
#1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4
#1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4
#1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4
#1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4
#1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4
#1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4
#1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4
#1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4
#1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4
#1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4
#1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4
#1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4
#1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4
#1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4
#1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4
#1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4
#1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4
#1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4
#1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4
#1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4
#1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4
#1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4
#1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4
#1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4
#1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4
#1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4
#1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4
#1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4
#1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4
#1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4
#1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4
#1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4
#1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4
#1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4
#1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4
#1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4
#1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4
#1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4
#1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4
#1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4
#1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4
#1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4
#1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4
#1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4
#1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4
#1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4
#1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4
#1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4
#1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4
#1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4
#1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4
#1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4
#1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4
#1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4
#1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4
#1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4
#1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4
#1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4
#1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4
#1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4
#1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4
#1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4
#1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4
#1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4
#1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4
#1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4
#1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4
#1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4
#1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4
#1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4
#1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4
#1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4
#1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4
#1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4
#1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4
#1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4
#1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4
#1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4
#1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4
#1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4
#1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4
#1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4
#1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4
#1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4
#1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4
#1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4
#1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4
#1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4
#1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4
#1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4
#1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4
#1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4
#1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4
#1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4
#1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4
#1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4
#1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4
#1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4
#2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4
#3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4
#3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4
#4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4
#5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4
#5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4
#6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4
#7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4
#7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4
#7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4
#8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4
#9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4

Continued:
I have updated the clock to have 600 MHz etc, same from the working project.
I have added the SEMC and QSPI FlexSPI pins in the config Tools.

I have also looked at the hex, and the Hex is not beeing generated correct:
Compared to the working project, my CustomHardware MCUExpresso IDE is leaving these address empty, when the document says it should be generated (https://www.nxp.com/docs/en/nxp/application-notes/AN12183.pdf)

I have added these hex values manually from the working project into the custom hardware Hex. It is still not running.

Why are these data not created for me? I have set the correct symbols related to XIP, the XIP_EXTERNAL_FLASH 1, XIP_BOOT_HEADER_ENABLE 1, and XIP_BOOT_HEADER_DCD_ENABLE 1.

Continued 2:
I have generated correct HEX now from MCUExpresso IDE with using XIP and XIP device in SDK manager. However still not entering main with Segger programmer debug JLINK, entering ResetISR().

Continued 3:
I have added the RT1050_SDRAM_Init.scp to use during debuggin, still no success.
I cannot read this, but here maybe someone can:

jeremyzhou · ‎07-05-2022

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Firstly, I'd like to suggest you check the custom board and assure the board is right, so you can refer to the attached hardware guide, further, you can use the NXP-MCUBootUtility tool to verify the FlexSPI connection.
Next, I'd like to know if the custom board contains the SDRAM besides the QSPI flash.
Have a great day,
TIC

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To provide the fastest possible support, I'd highly recommend you to refer to the post:

_bjs · ‎07-05-2022

Hello, Thank you for replying.
The custom hardware board i am using does have separate SDRAM. it is similar to the one on the IMXRT1050-EVKB.
We use the IS42S16160J-6TLI and the IMXRT1050-EVKB uses IS42S16160J-6BLI.

I believe the same SDRAM software on from the SDK should be useable to test. However the SEMC demo from the SDK is also not running on the IMXRT1050-EVKB.

Now i will try to make some parts of the SEMC demo to work, so i can test it.
And read into the NXP-MCUBootUtility tool, it is a lot of new information.

Continued:
Hello i have saved data to the FLASH!
For the NXP_MCUBootUtility tool i had to set the board into 'Serial Downloader' mode.
i swapped the 01 to 10 for boot modes, and i forgot about it, then i try to attempt iled-blinky again. It stored it because before i was already in 'serial downloader' and now i am in correct 'interal boot' mode.

I made mistake of thinking that for internal boot means SW7-3 High, SW7-Low. But when i set the SW7-3 Low and SW7-4 high, external Flash QSPI is working!

Thank you!

jeremyzhou · ‎07-06-2022

Thanks for your reply.
Firstly, there's a sdram demo in the SDK library for the EVKB-IMXRT1050 board, whose directory is ~\boards\evkbimxrt1050\driver_examples\semc\sdram.
Secondly, I've no idea whether you already use the NXP_MCUBootUtility tool to build a connection with the custom board successfully.
Have a great day,
TIC

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_bjs · ‎07-06-2022

Hello,
I have made progress the board can remember and program flash with the small iled-blinky example.

However when the program size is increasing i have the 0xDEADBEEE problem when trying to debug.
Do you know how to solve this?

jeremyzhou · ‎07-06-2022

Hi,
Thanks for your reply.
1）However when the program size is increasing i have the 0xDEADBEEE problem when trying to debug.
-- According to your reply, you can debug the simple demo project successfully now, is it right? And it encounters this problem on the condition that the size of the demo project increase, is it right too?
Have a great day,
TIC

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_bjs · ‎07-07-2022

Yes, when i am using SDRAM, during debugging the project will enter 0xDEADBEEE.
I tried the demo project of the SEMC, this is going successful, reading and writing.

I am now trying to do steps from: https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/I-MX-RT-How-to-booting-to-SDRAM/ta-p/1125054

I think i need to program flash, and on start up load the program into SDRAM? however my custom board will also use SDRAM to store EMWIN images/screens on.

I do not like the MCUBootUtilty and other programs/scripts, i prefer using the IDE and just SEGGER.

Do you have a tutorial of what and when SRAM_DTC, SRAM_ITC, SRAM_OC are need to be used? When which

When i increase my code to use a bit more function, the program will enter 0xDEADBEEE:

<- cannot run debugging

When the size is like this, it will work.

<- can run debugging,

So both Flash and SDRAM are different (NO SDRAM!), where flash difference is way bigger. maybe the problem is the flash?
Is there a limit of QSPI flash size in XIP or DCD default in IMXRT1050-EVKB demo projects?

jeremyzhou · ‎07-07-2022

Hi,
Thanks for your reply.
1) Do you have a tutorial of what and when SRAM_DTC, SRAM_ITC, SRAM_OC are need to be used?
-- Maybe you can refer to the attachment.
2) Maybe the problem is the flash?
-- Actually, it's too early to draw this conclusion, and whether you can replicate the phenomenon on the IMXRT1050-EVKB.
3) Is there a limit of QSPI flash size in XIP or DCD default in IMXRT1050-EVKB demo projects?
-- No

Have a great day,
TIC

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_bjs · ‎07-07-2022

Hello Thank you for the reply.

I cannot see any attachment.

For the Flash, I believe there might be a limit introduced by SEGGER. We have purchased their external flash loader software which i need to modify, for now I will try to keep my software small so that I can further test the hardware.

Maybe SEGGER only allowing 1 sector to be programmed or something like this, i believe i saw it somewhere when I was researching if LPCXpresso LPC-Link 2 could be used as an alternative.