Hello,
I'm using following code for brownout detection. I included fsl_pmu.h and fsl_pmu.c in the code. However, I observed that IRQ is not getting served. Kindly suggest the corrections in the code.
void Brownout_Init(void){
//Enable 1.1V brownout circuitry in the LDO
PMU_1P1EnableBrownout(PMU, TRUE);
//Set LDO output voltage to 1.1V
PMU_1P1SetRegulatorOutputVoltage(PMU, 0x10);
//Set LDO brownout offset voltage to 0.175V
PMU_1P1SetBrownoutOffsetVoltage(PMU, 0x7);
//Enable LDO output
PMU_1P1EnableOutput(PMU, TRUE);
//Enable 2.5V brownout circuitry in the LDO
PMU_2P5nableBrownout(PMU, TRUE);
//Set LDO output voltage to 2.5V
PMU_2P5SetRegulatorOutputVoltage(PMU, 0x10);
//Set LDO brownout offset voltage to 0.175V
PMU_2P5SetBrownoutOffsetVoltage(PMU, 0x7);
//Enable LDO output
PMU_2P5EnableOutput(PMU, TRUE);
NVIC_EnableIRQ(PMU_EVENT_IRQn);
}
void ANATOP_EVENT0_IRQHandler(void)
{
const uint32_t status = PMU_GetStatusFlags(PMU);
// uint16_t result = 0;
if (status & kPMU_1P1BrownoutOnOutput)
{
// result = kPMU_1P1BrownoutOnOutput;
}
if (status & kPMU_2P5BrownoutOnOutput)
{
// result = kPMU_2P5BrownoutOnOutput;
}
}
I'm having one more doubt, in the User Manual it is said that -
The following bitfields are not applicable on this device, and
those corresponding bits are Reserved:
• in PMU_REG_COREn register:
• RAMP_RATE
• REG2_TARG
• REG1_TARG
• REG0_TARG
• in PMU_MISC1n register: IRQ_DIG_BO.
• in PMU_MISC2n register:
• REG2_STEP_TIME
• REG1_STEP_TIME
• REG0_STEP_TIME
• REG2_OK
• REG2_ENABLE_BO
• REG1_ENABLE_BO
I found similar bitfields are also available in the register - CCM_ANALOG_MISC2n and this register is shared with PMU. So may I use CCM_ANALOG_MISC2n, instead of using PMU_MISC2n register? And its support is available in fsl_pmu.c?
