ABI for M4/M7 dual core (117x)

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ABI for M4/M7 dual core (117x)

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Contributor III

We have a desire to use a single compilation  for both the M4 and M7 cores on a RT1176 based design.  This is mostly because large portions of the code are "shared" and compiling twice is a PITA.

1.  The IDE uses "thumb" for the demos.  Is there a reason why Thumb2 is not used?

2.  If we do not use double-precision float, can the M4 and M7 run the same thumb2 code?

2a.  If 2 is no, is there a gcc switch-set that will produce an object file that will run on both cores?

If there is a guidance document to instruction set selection for Cortex-M, flip a pointer.

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NXP TechSupport
NXP TechSupport

Hello Dave,

Hope you are doing well.

The RT117x is still in pre-production stage. Therefore we are not able to answer any questions in our public community domain. I'd recommend that you please contact your local distributor for further support on this matter.

Have a great week!

Best Regards,

Sabina

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Contributor III

Arm sez (see pic) the Cortex-M4 ISA would restrict us from the Cortex-M7 vector instructions only.

Confirm?

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