The document will introduce how to configure LPSPI clock on I.MXRT1050. The purpose is to help IMXRT customers better understand the clock tree and configure LPSPI clock in SDK.
Customer can configure LPSPI clock according to the following steps:
1 Select Source according to the clock tree.
2 Set LPSPI_CKL_SEL according to the register CCM_CBCMR.
3 Enable LPSPIn clock according to the register CCM_CCGR1.
4 Set clock gate according to register CCM_ANALOG_PFD_480n[PFDn_CLKGATE].
5 Set LPSPI_PODF according to register CCM_CBCMR.
6 Set TCR[PRESCALE] according to LPSPIx module.
7 Set CCR[SCKDIV] according to LPSPIx module.
The customer can get the value LPSPI_CLK according to the above steps
If the MCU is switched to low power idle mode, and only 24MHz OSC is working, PLL[1-5] are all disabled, PERIPH_CLK2_SEL=OSC.
My question is if I have LPPSI work, how to configure its clock? Thank you.
See also this document which gives a practical overview of the clock tree: https://www.utasker.com/docs/iMX/i.MX_RT_1021_uTasker.pdf
In the case of the LPSPI_CLK_ROOT the default is for the "system" PLL2 to be used as source, divided by 4, which gives a clock speed of 132MHz (the maximum that the LPSPI can use).However, if the PLL2 is bypassed the speed will be 24MHz/4 (6MHz). The pre-scaler can be adjusted between 1 and 8 to choose the exact frequency that is preferred (3MHz, 3.429MHz, 4MHz, 4.8MHz, 6MHz, 8MHz, 12MHz or 24MHz).
Mark[uTasker project developer for Kinetis and i.MX RT]
Thank you Mark, I'm working on RT1052, doesn't it have the same clock tree you attached (rt1021)? According to rt1050RM, LPSPI_CLK_ROOT can only source from PLL2 and PLL3, if the PLL2 is disabled (bypassed), why does it still have a 24MHz? If so, I can put RT1052 work in low power mode and keep LPSPI working at the same time. Thank you again Mark!
Sorry, I think I misunderstood your point, I meant shutting off PLL1-5, but not bypass, if so, doesn't it mean that LPSPI will not work for no clock source?
The i.MX RT 1052 has the same clock tree with regard to the LPSPI paths.
The PLL bypass is controlled by the BYPASS bit in the register CCM_ANALOG_PLL_SYS, which is set to '1' after a reset - this is not shown directly in the clock tree diagram in the reference manuals
This is the default state of PLL2: It is off and bypassed, meaning that there is 24MHz at its output.
When it is enabled one first turns on the PLL and waits for it to lock and stabilise, then one removes the bypass so that the output is stable at 528MHz.
_SET_REGISTER(CCM_ANALOG_PFD_528, (CCM_ANALOG_PFD_528_PFD2_CLKGATE | CCM_ANALOG_PFD_528_PFD1_CLKGATE | CCM_ANALOG_PFD_528_PFD0_CLKGATE)); // disable PFD outputsCCM_ANALOG_PLL_SYS = (CCM_ANALOG_PLL_SYS_POWERUP | CCM_ANALOG_PLL_SYS_ENABLE | CCM_ANALOG_PLL_SYS_BYPASS | CCM_ANALOG_PLL_SYS_DIV_SELECT); // power up the PLL, enable its output but don't yet remove its bypassCCM_ANALOG_PLL_SYS_NUM = 0; // ensure the fixed frequency (528MHz) is used
_WAIT_REGISTER_FALSE(CCM_ANALOG_PLL_SYS, CCM_ANALOG_PLL_SYS_LOCK); // wait for PLL2 to lock at 528MHz_CLEAR_REGISTER(CCM_ANALOG_PLL_SYS, CCM_ANALOG_PLL_SYS_BYPASS); // clear the bypass
If LPSPI is clocked from PLL2 (528MHz) initially (divided by 4 to give max. 132MHz) its clock will reduce to 6MHz when the bypass is set and can be increased to 24MHz by then settings its pre-scaler to 1.
To use the 24MHz again one needs to bypass it again (and optionally turn off the PLL), but not before setting the LPSPI pre-scaler back to 4 , to avoid its clock root from being out of specification after PLL2 again at 528MHz.
What I don't know is whether your are switching automatically between the modes or whether you can control the sequences by code during the switching.
Note also that the LPSPI's default is 6MHz, which is explained by the default state discussed above:
Thanks Mark, you provided so detailed information. Now, I can get it bypassed and 24M OSC works for LPSPI.
One more question, my system was running in LOW POWER RUN mode but with 24M clock LPSPI, is it possible to make RT1050 go to LOW POWER IDLE mode? The NXP Application Note said all the PLLs should be disabled, does it mean that bypass is not allowed either? Actually, what I want is that RT1050 works in LOW POWER RUN mode normally and goes to LOW POWER IDLE if nothing to do (MCU is in WFI), but if LPSPI is always working (keep PLL2 bypassing), is it able to go to LOW POWER IDLE mode?
I don't yet have enough experience with the low power modes to be able to give a definitive answer but the bypass works with the PLL disabled so I expect that there will be no problem with this mode.
OK, thanks Mark.