imx 1024: where to specify the size of Flash B1

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imx 1024: where to specify the size of Flash B1

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bp1979
Senior Contributor I

In the reference manual we can read:

bp1979_0-1703011156173.png

I am trying to understand what this means exactly.

In SDK examples for the 1024 xip bytes are configuring flash as follows:

bp1979_1-1703011317564.png

So this seems to be correct, the SDK examples configure readSampleClkSrc to kFlexSPIReadSampleClk_LoopbackInternally (and not to kFlexSPIReadSampleClk_LoopbackFromDqsPad).

If I would set it to kFlexSPIReadSampleClk_LoopbackFromDqsPad, the SDK example still boots. So what does that tell me? Is this information ignored by ROM? Is it overruled by ROM? Because we need to enable flash B, which I THINK should be configured in these XIP bytes (by changing flexspi_nor_config.c) by defining a size for flash B directly after line 37.

Is that correct? Can you please shed some light on how ROM for the 1024 deals with these XIP bytes? Are they used? Ignored? Overruled by defaults? Or partly ignored/overruled?

Furthermore, in the SystemInit function called during startup code, these same XIP bytes are read from flash, and DQS, clock source, and flash frequency are "overwritten" / "forced".

So where should I specify the size of flash B1? In flexspi_nor_config.c? In the startup code / SystemInit? Both? Something else?

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @bp1979 ,

     Just as the RM mentioned, the FlexSPI_A_DQS pad is not supported by ROM
natively in RT1024, which restricts the maximum FLASH frequency to 60MHz.

   If you configure it to the kFlexSPIReadSampleClk_LoopbackFromDqsPad, which it still works, because it is still in 60Mhz, if you use higher frequency, it will have issues.

   If you want to change the loopback mode, you can refer to SDK code:

SDK_2_14_0_MIMXRT1024-EVK\boards\evkmimxrt1024\driver_examples\flexspi\nor\polling_transfer

Here, this will use the flexSPI register method to control it, it will be more clear.

You can change the RX sample clock situation, you also can change the FLASH PORT to the B Port, which is defined in the app.h:

#define FLASH_PORT kFLEXSPI_PortA1

#define EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad

For the XIP, FCB just support from A port, can't from B port, as the ROM define the A port:

kerryzhou_0-1703138592266.png

So, if you need to use the B port, you need to use my mentioned above code:

kerryzhou_0-1703138835104.png

 

 

Wish it helps you!
Best Regards,

Kerry

 

 

 

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bp1979
Senior Contributor I

Hi @kerryzhou 

Happy to see you on this topic! Thanks.

A lot if getting clearer while i digest more and more from manual and experiment with custom board/evks and getting answers on the forum.

Can you explain me exactly where to define the size for B1 flash? I thought it should be added in the xip config bytes, but after reading your reply I am no longer sure.

const flexspi_nor_config_t qspiflash_config = {
    .memConfig =
        {
            .tag                  = FLEXSPI_CFG_BLK_TAG,
            .version              = FLEXSPI_CFG_BLK_VERSION,
            .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally,
            .csHoldTime           = 3u,
            .csSetupTime          = 3u,
            .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
            .deviceType           = kFlexSpiDeviceType_SerialNOR,
            .sflashPadType        = kSerialFlash_4Pads,
            .serialClkFreq        = kFlexSpiSerialClk_60MHz,
            .sflashA1Size         = 4u * 1024u * 1024u,
	        .sflashB1Size         = 8u * 1024u * 1024u, // DO I DEFINE b1 size here
            .lookupTable =
                {

Many thanks in advance!

 

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mjbcswitzerland
Specialist V

Hi

mjbcswitzerland_0-1703180942708.png

Can someone specify which reference needs to be imported in order to find this?

Regards

Mark

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1,206 Views
mjbcswitzerland
Specialist V

Hi

The BOOT ROM only configures the FlexSPI A (based on the flash configuration values if finds).

When FlexSPI B is used the application needs to configure everything (The pins, FlexSPI registers, LUT, etc.) and so the SDK references are sited as reference to how to do it.

Regards

Mark


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bp1979
Senior Contributor I

Hi @mjbcswitzerland 

Just a short summary, to explain where we are in our journey of getting our second flash working:

- we have a custom board (with an IMX RT 1024), where secondary flash module is connected to FlexSPI port B

- the pin normally used for DQS for FlexSPI A1 (SD_B1_05) is used for SS0 on flash B in our schema

- so we have no other option to mux SD_B1_05 for FlexSPI B SS0, and thus accept the clock frequency of 60 MHz for both flashes

We are attempting to get a proof of life in the nor transfer polling example. Our current set of changes in this SDK example are:

1. disable FlexSPI A DQS muxing

The IMX RT 1024 has a weird difference compared to any other CPU in the IMX RT family as for as I know; something funky with ROM code not supporting DQS natively. Why, I don't know, but to compensate for this, the SDK examples mux DQS in the startup code. Since we need SD_B1_05 for second flash (B1), I commented out this line in the Startup/SystemInit.

    /* Configure FLEXSPI_A_DQS */
    // Commented out, we need SD_B1_05 for FlexSPI B SS0 function
    // IOMUXC -> SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);

2. Set flex spi clock to 60 MHz

Since we can't use DQS for Flash A, we must ensure that flex spi clock runs at 60 MHz). For this, we need to that the sample clock source is set to loopback internally (instead of LoopbackFromDqsPad), and set the clock to 60 MHz. For the 1024, this is also "overriden" in startup code in the SystemInit function. So same file, another small change:

    /* Re-Configure FLEXSPI NOR via ROM API, for details please refer to the init function of ROM FLEXSPI NOR flash
       driver which is in fsl_romapi.h and fsl_romapi.c in the devices\${soc}\drivers directory of SDK package */
    uint8_t flexspi_nor_config[512];
    memcpy((void *)flexspi_nor_config, (void *)FLASH_CONFIG_ADDRESS, sizeof(flexspi_nor_config));
    // Original values in SDK example
    // flexspi_nor_config[12] = 1U;  /* kFLEXSPIReadSampleClk_LoopbackFromDqsPad */
    // flexspi_nor_config[70] = 7U;  /* kFLEXSPISerialClk_133MHz */
    flexspi_nor_config[12] = 0U;  /* kFLEXSPIReadSampleClk_LoopbackInternally */
    flexspi_nor_config[70] = 1U;  /* kFLEXSPISerialClk_69MHz */

    flexspi_nor_init_t  flash_init = (flexspi_nor_init_t)ROM_FLASH_INIT_ADDRESS;
    flash_init(0U, flexspi_nor_config);
#endif /* #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) */

 

Next to that, I configured the pins for flexspi B in the pin tool, and had it generate the muxing in pinmux.c

IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA03,  /* GPIO_SD_B1_00 is configured as FLEXSPI_B_DATA03 */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_SCLK,    /* GPIO_SD_B1_01 is configured as FLEXSPI_B_SCLK */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA00,  /* GPIO_SD_B1_02 is configured as FLEXSPI_B_DATA00 */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA02,  /* GPIO_SD_B1_03 is configured as FLEXSPI_B_DATA02 */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_DATA01,  /* GPIO_SD_B1_04 is configured as FLEXSPI_B_DATA01 */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
  IOMUXC_SetPinMux(
      IOMUXC_GPIO_SD_B1_05_FLEXSPI_B_SS0_B,   /* GPIO_SD_B1_05 is configured as FLEXSPI_B_SS0_B */
      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
  

 

And finally, I adapted the more obvious required changes in the SDK example "user code".

- In app.h I selected FlexSPI port B1, and loopback internally.

#define EXAMPLE_FLEXSPI                 FLEXSPI
#define FLASH_SIZE                      0x1000 /* 32Mb/KByte */
#define EXAMPLE_FLEXSPI_AMBA_BASE       FlexSPI_AMBA_BASE
#define FLASH_PAGE_SIZE                 256
#define EXAMPLE_SECTOR                  6
#define SECTOR_SIZE                     0x1000 /* 4K */
#define EXAMPLE_FLEXSPI_CLOCK           kCLOCK_FlexSpi
#define FLASH_PORT                      kFLEXSPI_PortB1 /* was kFLEXSPI_PortA1 */
#define EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackInternally /* was kFLEXSPI_ReadSampleClkLoopbackFromDqsPad */ 

- In the flexspi_nor_polling_transfer.c (the "main" of the SDK example) I specified the clock speed of 60MHz

flexspi_device_config_t deviceconfig = {
    .flexspiRootClk       = 60000000, // was 133000000
    .flashSize            = FLASH_SIZE,
    .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
    .CSInterval           = 2,
    .CSHoldTime           = 3,
    .CSSetupTime          = 3,
    .dataValidTime        = 0,
    .columnspace          = 0,
    .enableWordAddress    = 0,
    .AWRSeqIndex          = 0,
    .AWRSeqNumber         = 0,
    .ARDSeqIndex          = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
    .ARDSeqNumber         = 1,
    .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
    .AHBWriteWaitInterval = 0,
};

You wrote:

"When FlexSPI B is used the application needs to configure everything (The pins, FlexSPI registers, LUT, etc.) and so the SDK references are sited as reference to how to do it."

So far I think I have all bases covered. The pins for FlexSPI B are muxed, the LUT is provided by the SDK example. They are the same for our flash (we used the flash module shipped with the 1021 EVK as secondary flash).

Except, I still don't know how to tell FlexSPI that I have a second flash module, and that this module is 8MB large. So I thought the only option was to configure this in the XIP bytes, which also specifies the size of flash A, since that struct allows me to also specify the size for flash B1.

const flexspi_nor_config_t qspiflash_config = {
    .memConfig =
        {
            .tag                  = FLEXSPI_CFG_BLK_TAG,
            .version              = FLEXSPI_CFG_BLK_VERSION,
            .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally,
            .csHoldTime           = 3u,
            .csSetupTime          = 3u,
            .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
            .deviceType           = kFlexSpiDeviceType_SerialNOR,
            .sflashPadType        = kSerialFlash_4Pads,
            .serialClkFreq        = kFlexSpiSerialClk_60MHz,
            .sflashA1Size         = 4u * 1024u * 1024u,
			.sflashB1Size		  = 8u * 1024u * 1024u, // I understand now that this is wrong!
            .lookupTable =

I now understand this is incorrect. But I still don't know where I should specify it.

What am I still missing?

 

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mjbcswitzerland
Specialist V

Hi

I made a mistake in thinking that the RT1024 had two FlexSPI controllers (like the RT1064) whereby it only has one.
This means that the flash configuration is valid (this is the configuration you have changed) for the single controller and is needed for it to boot from the internal Flash, which is using the FlexSPI's first chip select line. Basically I don't think you can, or need to, change it.

If you attach an external QSPI flash it is in fact on the same SPI bus as the internal chip (I suppose when the pins are configured to this mux mode it doesn't disconnect the internal chip but puts all lines in parallel) but the external chip needs to use the second chip select line.

Since I have done this only with the RT1064 (but on separate FlexSPI controllers since the internal one is FlexSPI2!) and the RT106x (using two QSPI flash devices on the external FlexSPI bus) I don't know exactly how it works with the RT1024 but I am assuming that it is approximately the same as the RT106x case (with one flash chip connected internally).

In that case the external pins will need to be configured (as they are initially not) but not the LUT if using the same chip type as the setting will be inherited from the boot setting.

Specifically, interpolating from my RT106x driver these are the instructions that I have that 'add' the second device on the bus.

_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_05, FLEXSPI_A_DQS, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_DQS on GPIO3-25 - alt function 1

_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_06, FLEXSPI_A_DATA03, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_DATA03 on GPIO3-26 - alt function 1
_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_07, FLEXSPI_A_SCLK, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_SCLK on GPIO3-27 - alt function 1
_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_08, FLEXSPI_A_DATA00, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_DATA00 on GPIO3-28 - alt function 1
_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_09, FLEXSPI_A_DATA02, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_DATA02 on GPIO3-29 - alt function 1
_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_10, FLEXSPI_A_DATA01, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_DATA01 on GPIO3-30 - alt function 1

_CONFIG_PERIPHERAL_LOOPBACK(GPIO_SD_B1_01, FLEXSPI_A_SS1_B, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_6 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select FLEXSPI_A_SS1_B on GPIO3-21 - alt function 3

noting that it muxes FLEX_A_SS1_B and not FLEXSPI_A_SS0_B !


And it configures the FlexSPI details for the second device with

FLEX_SPI_FLSHA2CR0 = (SPI_DATA_FLASH_1_SIZE/1024); // flash size in KBytes
FLEX_SPI_FLSHA2CR1 = (FLEX_SPI_FLSHnCR1_CSINTERVAL_VALUE(2) | FLEX_SPI_FLSHnCR1_TCSH_VALUE(3) | FLEX_SPI_FLSHnCR1_TCSS_VALUE(3)); // flash parameters
FLEX_SPI_FLSHA2CR2 = (0); // operation items

Notice here that the second flash size is defined by setting the register FLEX_SPI_FLSHA2CR0 (the BOOT ROM will have already set the size to FLEX_SPI_FLSHA1CR0 based on the size it read from the flash configuration table when it booted). This potentially answers your question about how to configure the size.

After this configuration the FlexSPI will access either the first or the second Flash chip (via the CS lines) based on the address that it accesses at so there would be nothing more to actually configure.

Concerning FlexSPI A and B: I only know of the B being used for Hyper flash, making the bus 8 bits wide. But I can't exclude that there is the possibility of configuring the FlexSPI controller to supply two separate buses of 4 data bits instead - but, since I have never done that (if it is possible) I can't show a reference. But, if it is the case, I can imagine that (if configured to work like that) its operation will be different in the way that it controls the two buses based on the access address rather than the way that it controls two CS line on a shared bus. Although obviously quite different the concept is much the same since, once configured, it controls the addressing automatically.

Regards

Mark


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bp1979
Senior Contributor I

Hi @mjbcswitzerland 

First of all: thank you for all your input!! I am still digesting you latest reply, and you made some solid suggestions which might give a breakthrough.

I just wanted to point one thing out. Indeed, 1021/1024 (we have both) have 1 FlexSPI peripheral. From MIMXRT1024.h

/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral FLEXSPI base address */
#define FLEXSPI_BASE                             (0x402A8000u)
/** Peripheral FLEXSPI base pointer */
#define FLEXSPI                                  ((FLEXSPI_Type *)FLEXSPI_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS                       { FLEXSPI_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS                        { FLEXSPI }
/** Interrupt vectors for the FLEXSPI peripheral type */
#define FLEXSPI_IRQS                             { FLEXSPI_IRQn }
/* FlexSPI AMBA address. */
#define FlexSPI_AMBA_BASE                       (0x60000000U)
/* FlexSPI ASFM address. */
#define FlexSPI_ASFM_BASE                        (0x60000000U)
/* Base Address of AHB address space mapped to IP RX FIFO. */
#define FlexSPI_ARDF_BASE                        (0x7FC00000U)
/* Base Address of AHB address space mapped to IP TX FIFO. */
#define FlexSPI_ATDF_BASE                        (0x7F800000U)

So FlexSPI lives at 0x402A8000u.

The "AMBA" base is 0x6000 0000. No clue what AMBA stands for, but at least this seems to map the AHB address to the start of Flash in my case.

The part where you are slightly off (I think) is where you mention I need CS to select a flash module. According to the reference manual the 102x can access up to 4 different memory modules:

typedef enum _flexspi_port
{
    kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
    kFLEXSPI_PortA2,        /*!< Access flash on A2 port. */
#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
    kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
    kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
#endif
    kFLEXSPI_PortCount
} flexspi_port_t;

Our schematics are wiring up flash A1 and flash B1, which should be accessible without switching using CS.

In ROM code, all pins are muxed (except DQS then) for flash port A1.

In my SDK example, I muxed all pins for flash port B1.

A2 and B2 are not connected, so I never need to bother with CS/SS0 after startup.

At least, this is how I understand things on my end!

Coming back to the more interesting part of your reply, do I understand you correctly when I translate your reply like this:

- the "configuration" XIP bytes are used by ROM code

- the ROM code will not do anything with the size I provided for flash B1, as it is solely responsible to setup stuff for flash connected to port A1?

- which means I still have to setup FlexSPI so that it knows flash on B1 exists, and is 8MB large

- your suggestion is to write to these registers in application code (meaning, I do not have to do this before jumping to main?)

PS: If all this is true, any idea why the nor config struct has a field for the flashSizeB1? Is that "generic" and used for other imx CPUs then?

 

 

 

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mjbcswitzerland
Specialist V

Hi

As noted, I haven't used the FlexSPI in all possible configurations yet so I only know the two that I have used (plus 8 bit bus for Hyper flash which uses the data lines of two ports).

In any case there will be chip selects involved but if the two devices are on independent ports with their own complete set of signals the setups for both will be the same - only when the data bus is shared by two devices will each need to set up a different CS output.

Taking a closer look at the flash configuration it does look like the BOOT ROM may be able to set up multiple sizes:

{0,0}, // [0x048-0x04f] reserved for future use
(INTERNAL_QSPI_FLASH_SIZE), // [0x050-0x053] size of flash connected to A1 - internal QSPI flash
0, // [0x054-0x057] size of flash connected to A2
0, // [0x058-0x05b] size of flash connected to B1
0, // [0x05c-0x05f] size of flash connected to B2

This is from my own code (left at 0) but I have only ever been concerned with the first one so that it can boot since all other settings can be performed at run time and then there can be no surprises when things don't work as expected/hoped - I have no idea whether the BOOT ROM implements all of the possibly things that are defined. That it boots successfully is the main concern and then doing the rest in code means no potential risks relying on more complicated stuff that may or may not work or be buggy since never really used and tested before.

As long as the i.MX RT can start code in XiP the FlexSPI can be modified or reprogrammed at any time later (by start-up code or application or when commanded to do) - there is no requirement to do it immediately or before the application starts, unless it is necessary before the application can operate correctly.

Regards

Mark

 

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bp1979
Senior Contributor I

Hi @kerryzhou @mjbcswitzerland 

Thanks again for all your input, I am getting further, nanometer by nanometer which is frustrating as hell, but ok.... it's what it is.

Analyzing the SDK example further and diving deeper in the flex_spi driver I found at least one horrible side effect of the flexspi init. It clears all memory sizes as a final step of the init. Afterwards, it will setup the FlexSPI B1 port, which effectively leaves FlexSPI A1 dead in the water (with size 0).

 

 

    /* Reset flash size on all ports */
    for (i = 0; i < (uint32_t)kFLEXSPI_PortCount; i++)
    {
        base->FLSHCR0[i] = 0;
    }

 

 

So after fixing this, and letting i start from 1 instead of 0, I at least can now finally run the SDK example on our custom board.

Smoking gun #1

When I read the vendor ID on port B1, it gives 239, which is the vendor ID of theinternal flash. We connected the exact same memory type to B1 that is present on the 1021 EVK board. When we read the vendor ID on the 1021 EVK, we get 157.

Smoking gun #2

When I erase the fist sector on flash B1, it works. But when the SDK example reads back these bytes, it reads all 0x0 bytes instead of 0xFF bytes. So clearly something is still broken...

Given these starting points:

- I start the 1024 without configuring DQS

- I disabled the part in startup which muxes DQS

- I changed the bit in startup code that sets read sample clock to DQS, I changed it to loopback internally

- I changed the bit in startup code that sets flex spi clock to 133 MHz, I changed it to 60 MHz.

- I muxed all pins for FlexSPI B in pin config, hit update, verified the pins muxed in pinmux.c

- Our custom board wired FlexSPI B to the exact same flash which comes with a 1021 EVK

- I copied the custom LUT from nor polling transfer example from SDK 1021 example

- I fixed the "bug" in fsl_flexpi to leave size of Flash A1 as is

- Changed app.h as follows:

 

 

#define EXAMPLE_FLEXSPI                 FLEXSPI
#define FLASH_SIZE                      0x1000 /* 32Mb/KByte */
#define EXAMPLE_FLEXSPI_AMBA_BASE       (FlexSPI_AMBA_BASE + 0x400000) /* This must be the base address for Flash connected to B1*/
#define FLASH_PAGE_SIZE                 256
#define EXAMPLE_SECTOR                  0
#define SECTOR_SIZE                     0x1000 /* 4K */
#define EXAMPLE_FLEXSPI_CLOCK           kCLOCK_FlexSpi
#define FLASH_PORT                      kFLEXSPI_PortB1
#define EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackInternally

 

 

PS: Ignore the fact that flash size of flash B1 is 8MB, the example still assumes 4MB, but I don't care, shouldn't make a difference.

As I said earlier:

When I run the SDK example on our custom board, it runs, but after erasing it's expecting 0xFF bytes while it reads 0x0 bytes. So the memory in 0x60400000 is either not our flash, or something else went bonkers.... Why.... What else do I need to do to get this "supposedly trivial task" working :(.

Attempting to read from JLink confirms:

 

 

J-Link>mem32 0x60400000,10
60400000 = 00000000 00000000 00000000 00000000 
60400010 = 00000000 00000000 00000000 00000000 
60400020 = 00000000 00000000 00000000 00000000 
60400030 = 00000000 00000000 00000000 00000000 

 

 

 

I attached the nor polling project with all modifications. I hope you can explain what I am missing.

 

 

 

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