iMXRT1021 - HARDFAULT in BOARD_BootClockRUN().

[t_thurgood]

Hi,

We have experienced HARDFAULT issues at POR time. When trying alternative NOR flash chips or start-up configurations we would get an immediate hardfault in IAR debugger or standalone.

In the past we have had issues with some of the (unnecessary clock configs) and these have been removed from our build, but the latest problem was only "fixed" when this config was commented out in clock_configs.c...

// CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);

I would like to know what this PFD is actually doing in relation to our hardware?

And do you see any consequences of this change?

We are using an IMXRT1021 with NOR flash, some led drivers, ethernet port and an RF chip.

br,

Tony

[chriscowdery]

I am working with Tony on this one and I did the original work. The code is based on one of the FreeRTOS examples for the MIMX1020-EVK.

Probably freertos_generic.zip

I have just checked and it has this misconfigured (?) clock.

Chris.

[mjbcswitzerland · Accepted solution]

Tony

The default PFD2 output is 396MHz (with a fraction value of 24) so the call with a value of 18 is presumably setting the output to 528 MHz, like the main output.
PLL2-PFD2 is potentially connected to various peripherals, which have their own frequency limits and possibly something using this is clocked beyond specification.

See also the table of page 5 of https://www.utasker.com/docs/iMX/i.MX_RT_1021_uTasker.pdf

The question is whether you configured this to output this frequency or whether whatever code you are using/generating is doing it maybe by mistake?

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]

[arpad_toth]

Why doesn't the UI tool show the clock limit in clock tree? Like in ST's cube MX.

[t_thurgood]

Hi Mark,

Thanks for the quick response and the very useful information.

I believe that clock config came from the original evk setup. I will investigate its use in our project, using the clock diagrams.

best regards,

Tony