Is there any way to set an interrupt or otherwise count the number of ECC detections/corrections in cache? It is simple to do for RAM with flexram, but I cannot find a way to monitor the cache's ECC.
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Hi @paytonsX
I checked our AN13204, AN12077 and our RT1170 reference manual.
We can know, RT1170 ECC can support TCM, Cache, OCRAM, external memory.
From the register description, I think cache ECC error detection should use the same register as your mentioned flexRAM.
Eg, INT_SIG_EN used to enable the interrupt when the issue comes.
But I think, it is difficult to get that error issues, please check the AN13204, chapter 6 ECC error injection.
You can find the CM7 cache can't support the Error injection, so you can't simulate the issues to demonstrate, just need to wait for the real issues to come in.
So, about the setting for ECC cache interrupt, I think you still can refer to the flexram method.
Wish it helps you!
If you still have questions about it, please kindly let me know.
Best Regards,
Kerry
Hi @paytonsX
I checked our AN13204, AN12077 and our RT1170 reference manual.
We can know, RT1170 ECC can support TCM, Cache, OCRAM, external memory.
From the register description, I think cache ECC error detection should use the same register as your mentioned flexRAM.
Eg, INT_SIG_EN used to enable the interrupt when the issue comes.
But I think, it is difficult to get that error issues, please check the AN13204, chapter 6 ECC error injection.
You can find the CM7 cache can't support the Error injection, so you can't simulate the issues to demonstrate, just need to wait for the real issues to come in.
So, about the setting for ECC cache interrupt, I think you still can refer to the flexram method.
Wish it helps you!
If you still have questions about it, please kindly let me know.
Best Regards,
Kerry
I downloaded the routine AN13204SW demo_mecc by pressing AN13204, but did not execute ECC's interrupt program. I used the development board 1170-EVK. I also couldn't get into ECC interrupts using the examples in the SDK. Can you take a look at it?
log below:
&SCB->ITCMCR = e000ef90
&SCB->DTCMCR = e000ef94
SCB_ITCMCR_RMW_Msk = 2
SCB_DTCMCR_RMW_Msk = 2
MECC_example
MECCn->PIPE_ECC_EN bit 4 as ECC_EN should be set to be 1 by ROM.
MECC1->PIPE_ECC_EN: 0
MECC2->PIPE_ECC_EN: 0
MECC2->ERR_STATUS: 0
MECC2->ERR_STAT_EN: ffff
MECC_example
ecc1_single_bit_ecc, press any key to continue.
[Error injection]
address = 0x20240020
data = 0x11223344▒▒▒▒aabbccdd
[Touch]
Address = 0x20240020.
Begin:
Data = 0x11223344_aabbccdd.
End.
ecc1_multi_bit_ecc, press any key to continue.
[Error injection]
address = 0x20240028
data = 0x11223344▒▒▒▒aabbccdd
[Touch]
Address = 0x20240028.
Begin:
Data = 0x11223344_aabbccdd.
End.
ecc2_single_bit_ecc, press any key to continue.
[Error injection]
address = 0x202c0020
data = 0x11223344▒▒▒▒aabbccdd
[Touch]
Address = 0x202c0020.
Begin:
Data = 0x11223344_aabbccdd.
End.
ecc2_multi_bit_ecc, press any key to continue.
[Error injection]
address = 0x202c0028
data = 0x11223344▒▒▒▒aabbccdd
[Touch]
Address = 0x202c0028.
Begin:
Data = 0x11223344_aabbccdd.
End.
Demo end.