i.MX RT 1064 FlexSPI Instruction and Data Size Clarifications

[atak_e]

Hello,

I am using an i.MX RT 1064 MCU to connect to a Lattice FPGA over Quad SPI using NXP's FlexSPI controller. The FPGA is handling our peripheral devices and sending the measurements it gets from them to the MCU. 

After going through the MCU documentation, I have a few questions concerning the different FlexSPI instructions, their required sizes, and whether some instructions can be skipped. Apologies if I am asking too many questions, any help would be appreciated!

For documentation, I am using the 1064 Reference Manual (Document ID: IMXRT1064RM) and the 1064 Data Sheet (Document ID: IMXRT1064IEC).

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Questions:

In the Reference Manual's section 27.3.7.1, it states that the ADDRESS instruction must be 32 bits to have 4 SCLK cycles, but the included Flash Access Sequence example shows 32 bits being sent with 8 SCLK cycles (Figure 27-7).

Am I misunderstanding something with the description for the ADDRESS Instruction, or is there an issue with the description/diagram? In Quad SPI, how many bits are transferred in one SCLK cycle? 4 bits?

Can I only send 13 bits (or 16 if necessary to fill all lanes) in 4 SCLK cycles? I only require 13 bits for ADDRESS on the FPGA. Am I forced to send 32 bits in 8 SCLK cycles?

Is the MODE instruction required, or can I skip that and go straight to a dummy cycle? I will only be using SDR to communicate with the FPGA. 

When does the "Data Size Instruction" get sent? Is this before the dummy cycles? Is this a required instruction to be sent? I am only sending 16 bits of data both ways (to/from MCU).

In the READ/WRITE instruction modes, can I just receive/send 16 bits of data in 4 SCLK cycles or am I forced to send 32 bits in 8 cycles?

My questions might be answered by the "Table 27-4. Instruction set" but I am not sure if I understood the Bits/Bytes numbers in that table correctly.

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If anyone would like, I can include my Timing Diagram that shows what I understand so far. It includes the ENABLE, OPCODE, ADDRESS, DELAY, READ/WRITE states on it along with the timing requirements I sourced from the data sheet referenced above.

I am writing a state machine for the FPGA that is clock-cycle dependent on changing the states, so I need to make sure that the i.MX RT 1064's state matches the state on the FPGA controller. 

Also, are there any programming examples for using FlexSPI to connect to a FPGA? I checked the examples within MCUXpresso but they are for NOR chips.

Thank you,

Egemen

[jay_heng · Accepted solution]

1. About ADDRESS Instruction, SCLK cycles depends port pad number, address bit can be either 24bit or 32bit. if it is Normal SPI SDR mode (1Pad), then there will be 24/32 SCLK cycles. if it is QuadSPI SDR mode (4Pad), there will be 6/8 SCLK cycles. if it is OctalSPI SDR mode (8Pad), there will be 3/4 SCLK cycles.

2. Send 13 bits (or 16 if necessary to fill all lanes) in 4 SCLK cycles? If it is QuadSPI SDR mode, 4 SCLK cycles always mean 16bit address data:

-if you set 0x10 in ADDR Seq: then it will be low 13 real address bits + high 3 Zero bits (FlexSPI inserts it automatically when AHB access)

-if you set 0x0d in ADDR Seq: then it will be low 3 dummy bits + high 13 real address bits (AHB access)

3. MODE bit can be ignored if you don't want to enable Continuous read mode. you can go straight to a dummy cycle.

4.The value in Data Size Instruction is only used in IPG command data transfer, it is useless in AHB command data transfer

5.You can just receive/send 16 bits of data in 4 SCLK cycles if using IPG command data transfer

[atak_e]

Thank you for the explanations!

[jay_heng]

We don't have programming examples for using FlexSPI to connect to a FPGA, as there is no FPGA device in NXP EVK board.