i.MX RT 1060 - Using two flash devices in Zephyr

[francois14]

Hello

Our board has two quad NOR flashes. The first one is connected to flexspi PortA1, the second to PortB1.  We are using Zephyr V3.4.0.

The corresponding section of our device tree can be found below.

The code is executed from the flash located on PortA.

I want to write to the second flash (on PortB), but it actually writes to the first flash (PortA) instead. What did I miss??

Thanks so much, François

&flexspi {
status = "okay";
pinctrl-0 = <&pinmux_flexspi1>;
pinctrl-names = "default";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x402a8000 0x4000>,
<0x60000000 DT_SIZE_M(36)>;

/* Port A: Firmware program */
mx25l32: mx25l32333f@0 {
compatible = "nxp,imx-flexspi-nor";
size = <33554432>;
reg = <0>; /* A1 */
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [c2 20 16];
erase-block-size = <4096>;
write-block-size = <1>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(1920)>;
};
slot1_partition: partition@1F0000 {
label = "image-1";
reg = <0x001F0000 DT_SIZE_K(1920)>;
};
scratch_partition: partition@3D0000 {
label = "image-scratch";
reg = <0x003D0000 DT_SIZE_K(192)>;
};
};
};

/* Port B */

mx25l256: mx25l25645m@2 {
compatible = "nxp,imx-flexspi-nor";
size = <268435456>;
reg = <2>; /* B1 */
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [c2 20 19];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
data_0: partition@0 {
label = "data_0";
reg = <0x00000000 DT_SIZE_M(16)>;
};

data_1: partition@1000000 {
label = "data_1";
reg = <0x01000000 DT_SIZE_M(16)>;
};

};
};

};

[Gamma_qin]

Dear @jingpan @francois14 

lastly, I also encountered the similar issue using the mimxrt1062 to drive 2 QSPI flash which connect to two physical ports (FLEXSPIA1,FLEXSPIA2). And the write/read flash application comes from "Zephy/samples/driver/spi_flash". But the flash on FLEXSPIA2 could not read successfully? could you help me to have a look at this issue?

the select dts file as following shown:

&flexspi {

    status = "okay";

    pinctrl-0 = <&pinmux_flexspi1>;

    pinctrl-names = "default";

    ahb-prefetch;

    ahb-read-addr-opt;

    rx-clock-source = <1>;

    reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(32)>;

    mt25qu256: mt25qu256@0 {

        compatible = "nxp,imx-flexspi-nor";

        size = <33554432>;

        reg = <0>;

        spi-max-frequency = <133000000>;

        status = "okay";

        jedec-id = [20 bb 19];

        erase-block-size = <4096>;

        write-block-size = <1>;

        partitions {

            compatible = "fixed-partitions";

            #address-cells = <1>;

            #size-cells = <1>;

            boot_partition: partition@0 {

                label = "mcuboot";

                reg = <0x00000000 DT_SIZE_M(4)>;

            };

            slot0_partition: partition@400000 {

                label = "image-0";

                reg = <0x00400000 DT_SIZE_M(4)>;

            };

            slot1_partition: partition@800000 {

                label = "image-1";

                reg = <0x00800000 DT_SIZE_M(4)>;

            };

            scratch_partition: partition@B00000 {

                label = "image-scratch";

                reg = <0x00B00000 DT_SIZE_M(4)>;

            };

            storage_partition: partition@F00000 {

                label = "storage";

                reg = <0x00F00000 DT_SIZE_M(16)>;

            };

        };

    };

};

&flexspi2 {

    status = "okay";

    pinctrl-0 = <&pinmux_flexspi2>;

    pinctrl-names = "default";

    ahb-prefetch;

    ahb-read-addr-opt;

    ahb-bufferable;

    ahb-cacheable;

    sck-differential-clock;

    rx-buffer-config = <1 7 11 1024>;

    rx-clock-source = <1>;

    reg = <0x402a4000 0x3c00>, <0x70000000 DT_SIZE_M(32)>;

    mt25qu256_fpga: mt25qu256_fpga@1 {

        compatible = "nxp,imx-flexspi-nor-fpga";

        size = <DT_SIZE_M(32*8)>;

        reg = <1>;

        spi-max-frequency = <133000000>;

        status = "okay";

        jedec-id = [20 bb 19];

        erase-block-size = <4096>;

        write-block-size = <1>;

        partitions {

            compatible = "fixed-partitions";

            #address-cells = <1>;

            #size-cells = <1>;

            fpga_storage_partition: partition@0 {

                label = "storage";

                reg = <0x00000000 DT_SIZE_M(32)>;

            };

        };

    };

};

and the following image is the run  test result through UART.

[jingpan]

Hi @francois14 ,

FlexSPI select flash chip (/CS) according to the address. You can check the

FLEXSPI->FLSHA1CR0[FLSHSZ] register field to see if the size is correct.

Regards,

Jing

[francois14]

Thank you Jing

I can now trigger the CS pin, and CLK is correct too.

However with the code running in XIP mode from the flash connected to port A1, I get a strange signal on the D0/D1 lines of the second flash (connected to B1) when trying to access it. Picture below.

With the code running from RAM, the flash connected to B1 is working correctly. Any idea?

[jingpan]

Hi @francois14 ,

I think CS is more important. Is B1 CS goes low when the strange signal appear?

Regards,

Jing