Using NAND flash on iMX RT 1170 evk

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Using NAND flash on iMX RT 1170 evk

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FaroukBouabid
Contributor I

Hi, I am trying to use the NAND flash through SEMC on the iMX RT 1170 evaluation board and I couldn't help but notice that the resistors on the nand_data pins are not integrated. Is there a hardware modification that must be performed on this board in order to use the NAND flash and SDRAM in the same time ? Thx in advance, Best regards.

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jay_heng
NXP Employee
NXP Employee

NAND flash device is not enabled by default on RT1170 EVK board, you need to populate R1872~R1879 to enable NAND. and I have ever done NAND boot time test on EVK (https://www.cnblogs.com/henjay724/p/12591382.html)

As NAND device shares some same SEMC signals with SDRAM device (but with different CS), so it is not easy to use them in some case (for example, copying page data from NAND to SDRAM directly via AHB bus), but below case is ok:

NAND stores user application, after bootup, BootROM copies application from NAND to TCM, then application executes in TCM and configures SEMC to use SDRAM

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2,283 次查看
jay_heng
NXP Employee
NXP Employee

NAND flash device is not enabled by default on RT1170 EVK board, you need to populate R1872~R1879 to enable NAND. and I have ever done NAND boot time test on EVK (https://www.cnblogs.com/henjay724/p/12591382.html)

As NAND device shares some same SEMC signals with SDRAM device (but with different CS), so it is not easy to use them in some case (for example, copying page data from NAND to SDRAM directly via AHB bus), but below case is ok:

NAND stores user application, after bootup, BootROM copies application from NAND to TCM, then application executes in TCM and configures SEMC to use SDRAM

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FaroukBouabid
Contributor I

Thanks for your reply. As a particular use case, is using the NAND flash as a data storage media and the SDRAM for the application acceptable ?

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jay_heng
NXP Employee
NXP Employee

CPU fetches app instruction from SDRAM while app wants to read data from NAND via the same SEMC DQ[x:0], it is kind of hard to manage this case but SEMC supports it in theory.

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FaroukBouabid
Contributor I

Isn't Queue B supposed to manage SDRAM when A is overloaded with NAND requests ? (By application I didn't mean code : I meant data (Heap - stack))

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jay_heng
NXP Employee
NXP Employee

I just checked this case with SEMC designer, he said that this case was well supported by SEMC.

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