AN13364 describe PLL adjust method according SOF in RT600, but from demo usb_device_audio_speaker , API 'CTIME_SOF_TOGGLE_HANDLER_PLL' make me confused.
could someone explain it briefly?
Hi,
As the AN13364 points out in section 2.4 KL27 clock distribution, The format of USB audio device used in this example is a two-channel 48 K/24 bit data stream. If the I2S interface is configured as 48K/24 bit, the corresponding I2S_BCLK = 48 K * 24 * 2 = 2.034 M.
This is the I2S_BCLK clock route, assuming that the I2S clock divider is 1:
Assume that the input clock is 16m_irc, after the Audio PLL, Audio_PLL_Divider, the output clock is 2.034MHz. But the 16m_irc frequency is not accurate and subject to temperature, so the I2S_BCLK maybe is not 2.034mhz. for example, it is 2.03Mhz, in the case, more and more data will be blocked in the buffer.
You can use a Ctimer or SCTimer or whatever, which has capture function, you can connect the USB_Toggle signal to the capture pin of Ctimer or SCTimer, connect the I2S_BCLK to input pin of Ctimer or SCTimer as tick signal, the Ctimer or SCTimer can count the external I2S_BCLK and enable capture function. In the capture ISR of Ctimer or SCTime which is triggered by the 1KHz USB_Toggle signal, the captured value will be 2034. If the capture is not 2034, you can modify the fractional value of audio_PLL to change I2S_BCLK frequency, in the end, the I2S)BCLK will reach to 2.034MHz.
Hope I explain it clearly.
BR
XiangJun Rong
Hi,
As the AN13364 points out in section 2.4 KL27 clock distribution, The format of USB audio device used in this example is a two-channel 48 K/24 bit data stream. If the I2S interface is configured as 48K/24 bit, the corresponding I2S_BCLK = 48 K * 24 * 2 = 2.034 M.
This is the I2S_BCLK clock route, assuming that the I2S clock divider is 1:
Assume that the input clock is 16m_irc, after the Audio PLL, Audio_PLL_Divider, the output clock is 2.034MHz. But the 16m_irc frequency is not accurate and subject to temperature, so the I2S_BCLK maybe is not 2.034mhz. for example, it is 2.03Mhz, in the case, more and more data will be blocked in the buffer.
You can use a Ctimer or SCTimer or whatever, which has capture function, you can connect the USB_Toggle signal to the capture pin of Ctimer or SCTimer, connect the I2S_BCLK to input pin of Ctimer or SCTimer as tick signal, the Ctimer or SCTimer can count the external I2S_BCLK and enable capture function. In the capture ISR of Ctimer or SCTime which is triggered by the 1KHz USB_Toggle signal, the captured value will be 2034. If the capture is not 2034, you can modify the fractional value of audio_PLL to change I2S_BCLK frequency, in the end, the I2S)BCLK will reach to 2.034MHz.
Hope I explain it clearly.
BR
XiangJun Rong
