RT600 I2S/TDM Interface clocking

[ferringer1]

I have a question regarding the RT600 FlexComm Interface in I2S/TDM mode. I try to break it down as much as possible:

• Pinning:
  • CLK coming from outside
  • WS coming from outside (serves as start-of-frame in TDM mode) 
  • Bidir data communication with one TX and one RX pin, 48kHz, 16bit/word, 8 channels
• This results in a TDM-clock frequency of 16bit * 8 channels * 48kHz = 6.144MHz
• So the two FlexComms needed for full duplex both operate as slaves, one for RX, the other for TX, for 8 channels each

For various reasons, the external communication partner operates the interface at 10MHz with an independent clock.  This has two major implications:

1. There are "unused" clocks between the frames: One Frame is nominally 16bit*8channels = 128 clock cycles long. But at 10MHz it would be 10MHz/48kHz=208.3 cycles long. So there are about 80 unused clock cycles
2. In order to be in sync with the systemwide audio-clock and due to rounding errors (because of the fractional part of 208.3), the WS (start-of-frame) signal cannot be issued exactly every 208 clocks. Sometimes it might be 209, sometimes maybe even just 207 clocks apart.

The question is if this mode of operation is supported. I actually don't see any contradictions from the manual. Especially (1) shouldn't be a problem at all. With (2) I am not so sure, but I also think that TDM mode is capable of handling an "arbitrary amount of unused" clock cycles. According to the I2S spec, everything outside the nominal audio-bits is just ignored. But then this is not I2S but proprietary TDM.

Regards, Markus

[Omar_Anguiano]

Hello
I hope you are well. 

I don't see a contradiction on (1), the following frames can be ignored on application however I don't think (2) can be handled by the interface, one option I see is to switch the WS in GPIO to have control on were it ends. 

Best regards,
Omar

[ferringer1]

Thanks for the clarification. I am not entirely sure what you mean by "switch the WS in GPIO to have control on where it ends"

The point is that the WS signal along with the clock is provided by the external FPGA device. So I guess the question for (2) can be rephrased: When is the internal bit-counter of the TDM interface reset to 0?

If it's reset upon assertion of the WS signal (which makes sense), then everything should work fine: Additional bits after the active part of the frame are simply ignored, no matter how many. And assertion of the WS signal resets the counter and starts a new frame.